參數(shù)資料
型號： AM49DL3208G
英文描述： Am49DL3208G - Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM
中文描述： Am49DL3208G -堆疊式多芯片封裝（MCP）的閃存和移動存儲芯片
文件頁數(shù)： 54/62頁
文件大小： 933K
代理商： AM49DL3208G
52
Am49DL3208G
September 19, 2003
A D V A N C E I N F O R M A T I O N
PSEUDO SRAM AC CHARACTERISTICS
Power Up Time
When powering up the SRAM, maintain V
CC
s for 100 μs minimum with CE#1s at V
IH
.
Read Cycle
Notes:
1. CE1#s = OE# = V
IL
, CE2s = WE# = V
IH
, UB#s and/or LB#s = V
IL
2. Do not access device with cycle timing shorter than t
RC
for continuous periods < 10 μs.
Figure 30.
Pseudo SRAM Read Cycle—Address Controlled
Parameter
Symbol
Description
Speed
Unit
55
70
t
RC
Read Cycle Time
Min
55
70
ns
t
AA
Address Access Time
Max
55
70
ns
t
CO1
, t
CO2
Chip Enable to Output
Max
55
70
ns
t
OE
Output Enable Access Time
Max
30
35
ns
t
BA
LB#s, UB#s to Access Time
Max
55
70
ns
t
LZ1
, t
LZ2
Chip Enable (CE1#s Low and CE2s High) to Low-Z
Output
Min
5
ns
t
BLZ
UB#, LB# Enable to Low-Z Output
Min
5
ns
t
OLZ
Output Enable to Low-Z Output
Min
5
ns
t
HZ1
, t
HZ2
Chip Disable to High-Z Output
Max
20
25
ns
t
BHZ
UB#s, LB#s Disable to High-Z Output
Max
20
25
ns
t
OHZ
Output Disable to High-Z Output
Max
20
25
ns
t
OH
Output Data Hold from Address Change
Min
10
ns
Address
Data Out
Previous Data Valid
Data Valid
t
AA
t
RC
t
OH
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