參數(shù)資料
型號(hào)： AM49DL3208G
英文描述： Am49DL3208G - Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM
中文描述： Am49DL3208G -堆疊式多芯片封裝（MCP）的閃存和移動(dòng)存儲(chǔ)芯片
文件頁(yè)數(shù)： 5/62頁(yè)
文件大?。?/td> 933K
代理商： AM49DL3208G
September 19, 2003
Am49DL3208G
3
A D V A N C E I N F O R M A T I O N
TABLE OF CONTENTS
Product Selector Guide. . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5
Flash memory Block Diagram . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . 7
Special Package Handling Instructions ....................................7
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 9
MCP Device Bus Operations. . . . . . . . . . . . . . . . . 9
Table 1. Device Bus Operations .....................................................10
Flash Device Bus Operations . . . . . . . . . . . . . . . 10
Requirements for Reading Array Data ...................................10
Writing Commands/Command Sequences ............................11
Accelerated Program Operation ......................................................11
Autoselect Functions .......................................................................11
Simultaneous Read/Write Operations with Zero Latency .......11
Standby Mode ........................................................................11
Automatic Sleep Mode ...........................................................12
RESET#: Hardware Reset Pin ...............................................12
Output Disable Mode ..............................................................12
Table 2. Top Boot Sector Addresses ............................................. 12
Table 3. Top Boot SecSi
Sector Addresses ............................... 14
Table 4. Bottom Boot Sector Addresses......................................... 14
Table 5. Bottom Boot SecSi
Sector Addresses.......................... 15
Sector/Sector Block Protection and Unprotection ..................16
Table 6. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection ............................................................. 16
Table 7. Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection ............................................................. 16
Write Protect (WP#) ................................................................17
Temporary Sector Unprotect ..................................................17
Figure 1. Temporary Sector Unprotect Operation ...........................17
Figure 2. In-System Sector Protect/Unprotect Algorithms ..............18
SecSi (Secured Silicon) Sector
Flash Memory Region ............................................................19
Figure 3. SecSi Sector Protect Verify ..............................................20
Hardware Data Protection ......................................................20
Low V
CC
Write Inhibit .......................................................................20
Write Pulse “Glitch” Protection ........................................................20
Logical Inhibit ..................................................................................20
Power-Up Write Inhibit ....................................................................20
Common Flash Memory Interface (CFI). . . . . . . 20
Table 8. CFI Query Identification String ..........................................21
Table 9. System Interface String..................................................... 22
Table 10. Device Geometry Definition ............................................22
Table 11. Primary Vendor-Specific Extended Query ......................23
Flash Command Definitions . . . . . . . . . . . . . . . . 24
Reading Array Data ................................................................24
Reset Command .....................................................................24
Autoselect Command Sequence ............................................24
Enter SecSi Sector/Exit SecSi Sector
Command Sequence ..............................................................24
Word Program Command Sequence .....................................25
Unlock Bypass Command Sequence ..............................................25
Figure 4. Program Operation ..........................................................26
Chip Erase Command Sequence ...........................................26
Sector Erase Command Sequence ........................................26
Erase Suspend/Erase Resume Commands ...........................27
Figure 5. Erase Operation ...............................................................27
Table 12. Command Definitions ..................................................... 28
Flash Write Operation Status. . . . . . . . . . . . . . . . 29
DQ7: Data# Polling .................................................................29
Figure 6. Data# Polling Algorithm .................................................. 29
RY/BY#: Ready/Busy# ............................................................30
DQ6: Toggle Bit I ....................................................................30
Figure 7. Toggle Bit Algorithm ........................................................ 30
DQ2: Toggle Bit II ...................................................................31
Reading Toggle Bits DQ6/DQ2 ...............................................31
DQ5: Exceeded Timing Limits ................................................31
DQ3: Sector Erase Timer .......................................................31
Table 13. Write Operation Status................................................... 32
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 33
Figure 8. Maximum Negative Overshoot Waveform ...................... 33
Figure 9. Maximum Positive Overshoot Waveform ........................ 33
Flash DC Characteristics . . . . . . . . . . . . . . . . . . . 34
CMOS Compatible ..................................................................34
Figure 10. I
CC1
Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 35
Figure 11. Typical I
vs. Frequency ............................................ 35
Pseudo SRAM DC and
Operating Characteristics . . . . . . . . . . . . . . . . . . 36
Figure 12. Standby Current ISB CMOS ......................................... 37
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 13. Test Setup .................................................................... 38
Figure 14. Input Waveforms and Measurement Levels ................. 38
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
Pseudo SRAM CE#s Timing ...................................................39
Figure 15. Timing Diagram for Alternating
Between Pseudo SRAM and Flash ................................................ 39
Read-Only Operations ...........................................................40
Figure 16. Read Operation Timings ............................................... 40
Hardware Reset (RESET#) ....................................................41
Figure 17. Reset Timings ............................................................... 41
Word Configuration ................................................................42
Figure 18. CIOf Timings for Read Operations ................................ 42
Figure 19. CIOf Timings for Write Operations ................................ 42
Flash Erase and Program Operations ....................................43
Figure 20. Program Operation Timings .......................................... 44
Figure 21. Accelerated Program Timing Diagram .......................... 44
Figure 22. Chip/Sector Erase Operation Timings .......................... 45
Figure 23. Back-to-back Read/Write Cycle Timings ...................... 46
Figure 24. Data# Polling Timings (During Embedded Algorithms) . 46
Figure 25. Toggle Bit Timings (During Embedded Algorithms) ...... 47
Figure 26. DQ2 vs. DQ6 ................................................................. 47
Temporary Sector Unprotect ..................................................48
Figure 27. Temporary Sector Unprotect Timing Diagram .............. 48
Figure 28. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 49
Alternate CE#f Controlled Erase and Program Operations ....50
Figure 29. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings .......................................................................... 51
Pseudo SRAM AC Characteristics . . . . . . . . . . . 52
Power Up Time .......................................................................52
Read Cycle .............................................................................52
Figure 30. Pseudo SRAM Read Cycle—Address Controlled ......... 52
Figure 31. Pseudo SRAM Read Cycle ........................................... 53
Write Cycle .............................................................................54
Figure 32. Pseudo SRAM Write Cycle—WE# Control ................... 54
Figure 33. Pseudo SRAM Write Cycle—CE1#s Control ................ 55
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