參數(shù)資料
型號： AM49DL3208G
英文描述： Am49DL3208G - Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM
中文描述： Am49DL3208G -堆疊式多芯片封裝（MCP）的閃存和移動存儲芯片
文件頁數(shù)： 12/62頁
文件大?。?/td> 933K
代理商： AM49DL3208G
10
Am49DL3208G
September 19, 2003
A D V A N C E I N F O R M A T I O N
Table 1.
Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 11.5–12.5
V, X = Don’t Care, SADD = Flash Sector Address, A
IN
=
Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = V
IL
, CE1#s = V
IL
and CE2s = V
IH
at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = V
IL
, the boot sectors will be protected. If WP#/ACC = V
IH
the boot sectors protection will be removed.
If WP#/ACC = V
ACC
(9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
6. If WP#/ACC = V
, the two outermost boot sectors remain protected. If WP#/ACC = V
, the two outermost boot sector protection
depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and
Unprotection”. If WP#/ACC = V
HH,
all sectors will be unprotected.
FLASH DEVICE BUS OPERATIONS
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE#f and OE# pins to V
IL
. CE#f is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
IH
. The CIOf pin determines
whether the device outputs array data in words or
bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
Operation
(Notes 1, 2)
CE#f
CE1#s
CE2s OE# WE#
Addr.
LB#s UB#s RESET#
WP#/ACC
(Note 4)
DQ7–
DQ0
DQ15–
DQ8
Read from Flash
L
H
X
L
H
A
IN
X
X
H
L/H
D
OUT
D
OUT
X
L
Write to Flash
L
H
X
H
L
A
IN
X
X
H
(Note 4)
D
IN
D
IN
X
L
Standby
V
CC
±
0.3 V
H
X
X
X
X
X
X
V
CC
±
0.3 V
H
High-Z
High-Z
X
L
Output Disable
L
L
H
H
H
X
L
X
H
L/H
High-Z
High-Z
H
H
X
X
L
Flash Hardware
Reset
X
H
X
X
X
X
X
X
L
L/H
High-Z
High-Z
X
L
Sector Protect
(Note 5)
L
H
X
H
L
SADD,
A6 = L,
A1 = H,
A0 = L
X
X
V
ID
L/H
D
IN
X
X
L
Sector Unprotect
(Note 5)
L
H
X
H
L
SADD,
A6 = H,
A1 = H,
A0 = L
X
X
V
ID
(Note 6)
D
IN
X
X
L
Temporary Sector
Unprotect
X
H
X
X
X
X
X
X
V
ID
(Note 6)
D
IN
High-Z
X
L
Read from PSRAM
H
L
H
L
H
A
IN
L
L
H
X
D
OUT
High-Z
D
OUT
D
OUT
High-Z
H
L
L
H
D
OUT
D
IN
High-Z
Write to PSRAM
H
L
H
X
L
A
IN
L
L
H
X
D
IN
D
IN
H
L
L
H
D
IN
High-Z
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