參數(shù)資料
型號(hào)： AM49DL3208G
英文描述： Am49DL3208G - Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM
中文描述： Am49DL3208G -堆疊式多芯片封裝（MCP）的閃存和移動(dòng)存儲(chǔ)芯片
文件頁(yè)數(shù)： 42/62頁(yè)
文件大?。?/td> 933K
代理商： AM49DL3208G
40
Am49DL3208G
September 19, 2003
A D V A N C E I N F O R M A T I O N
FLASH AC CHARACTERISTICS
Read-Only Operations
Notes:
1. Not 100% tested.
2. See
Figure 13
and
Table 14
for test specifications
3. Measurements performed by placing a 50
termination on the data pin with a bias of V
CC
/2. The time from OE# high to the
data bus driven to V
CC
/2 is taken as t
DF
.
Parameter
Description
Test Setup
All Speed
Options
JEDEC
Std.
Unit
t
AVAV
t
RC
Read Cycle Time (Note 1)
Min
70
ns
t
AVQV
t
ACC
Address to Output Delay
CE#f, OE# = V
IL
Max
70
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE# = V
IL
Max
70
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
30
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (Notes 1, 3)
Max
16
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Notes 1, 3)
Max
16
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE#f or
OE#, Whichever Occurs First
Min
0
ns
t
OEH
Output Enable Hold Time
(Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
t
OH
t
CE
Outputs
WE#
Addresses
CE#f
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
t
RC
t
ACC
t
OEH
t
RH
t
OE
t
RH
0 V
RY/BY#
RESET#
t
DF
Figure 16.
Read Operation Timings
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