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參數(shù)資料
| 型號： | AM30LV0064D |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology |
| 中文描述： | 64兆位（8米× 8位）的CMOS 3.0伏特，只有UltraNAND閃存技術(shù) |
| 文件頁數(shù)： | 13/41頁 |
| 文件大小： | 1067K |
| 代理商： | AM30LV0064D |
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Am30LV0064D
13
DEVICE BUS OPERATIONS, COMMAND
SET, AND COMMAND DEFINITIONS
This section describes the requirements and use of
the device bus operations, the command set, and the
command definitions. The device bus operations are
initiated through the internal command register which
decodes the command to determine the current opera-
tion to be performed. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine whose outputs dictate the function of the device.
Table 2 lists the device bus operations including the in-
puts and control levels they require, and the resulting
output. Table 3 lists the command set, and Table 4 lists
the command definitions. The “Device Operations”
section describes each of these operations in detail.
Table 2. Am30LV0064D Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, X = Don’t Care, A
IN
= Address In, C
IN
= Command In, D
IN
= Data In, D
OUT
= Data Out
Note:
If WP# = V
IL
, the Flash device is protected and will not allow program or erase operations to occur. If WP# = V
IH
, the
device is unprotected and may be programmed or erased.
Table 3. Am30LV0064D Command Set
Operation
CE#
RE#
WE#
SE#
CLE
ALE
WP#
I/O7–I/O0
Read Data Area
L
L
H
L/H
L
L
X
D
OUT
Read Spare Area
L
L
H
L
L
L
X
D
OUT
Read ID, Status
L
L
H
X
L
L
X
D
OUT
Write Data
L
H
L
L/H
L
L
X
D
IN
Write Command
L
H
L
X
H
L
X
C
IN
Write Address
L
H
L
X
L
H
X
A
IN
Standby
V
CC
±
0.3 V
X
X
V
CC
±
0.3 V
V
SS
±
0.3 V
X
X
V
CC
±
0.3 V
V
SS
±
0.3 V
High-Z
Write Protect
X
X
X
X
X
X
(See Note)
X
Operation
Cycle 1
Cycle 2
Valid During Busy
Read Data
00h/01h
–
No
Gapless Read
02h
–
No
Read Spare Area
50h
–
No
Read ID
90h
–
No
Read Status
70h
–
Yes
Input Data
80h
–
No
Page Program
10h
–
No
Block Erase
60h
D0h
No
Erase Suspend
B0h
–
Yes
Erase Resume
D0h
–
No
Reset
FFh
–
Yes
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| AM30LV0064DJ40 | 64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AM30LV0064DJ40 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology |
| AM30LV0064DJ40E21 | 制造商:Advanced Micro Devices 功能描述: |
| AM30LV0064DJ40E2I | 制造商:Advanced Micro Devices 功能描述:NAND Flash Parallel 3V/3.3V 64Mbit 8M x 8bit 35ns 44-Pin TSOP |
| AM30LV0064DJ40E2IT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology |
| AM30LV0064DJ40F2I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NAND Flash EEPROM |
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