參數(shù)資料
型號(hào)： AM30LV0064D
廠商： Advanced Micro Devices, Inc.
英文描述： 64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology
中文描述： 64兆位（8米× 8位）的CMOS 3.0伏特，只有UltraNAND閃存技術(shù)
文件頁數(shù)： 10/41頁
文件大?。?/td> 1067K
代理商： AM30LV0064D
10
Am30LV0064D
FUNCTIONAL PIN DESCRIPTION
Input/Output Pins (I/O7–I/O0)
The eight I/O pins are used to send commands, ad-
dresses, and data to the device, and to receive data
during read operations.
Command Latch Enable (CLE)
The CLE input controls activation of the command reg-
ister for the receipt of commands. When CLE is high,
the command is latched into the command register on
the rising edge of the Write Enable (WE#) signal.
Address Latch Enable (ALE)
The ALE input controls activation of the address register
during the address latch operation, or the data register
during the Input Data operation. When ALE is high, the
address information is latched on the rising edge of
the Write Enable (WE#) signal. When ALE is low (and
the CLE input is low) the Input Data information is
latched on the rising edge of the Write Enable (WE#)
signal. ALE must remain high for the entire address
sequence or device will reset.
Chip Enable (CE#)
The CE# input controls the active/standby mode dur-
ing command, data, and address inputs. During the
command and address latch operations, CE# must be
low prior to the falling edge of Write Enable (WE#).
During Input Data operations, CE# must remain low
until after the rising edge of WE# during the final Data
In operation. When CE# is high, and an internal opera-
tion is not in process, the device goes into standby
mode and current consumption is greatly reduced.
The CE# signal is ignored during program or erase op-
eration, as indicated by the Busy state (RY/BY# =
low).
Read Enable (RE#)
The RE# input controls the serial data output and sta-
tus from the I/O lines. The data output is triggered on
the falling edge of RE#, with valid data available after
a delay of t
REA
. The Status output data is also triggered
on the falling edge of RE#, with the status available
after a delay of t
RLS
.
Write Enable (WE#)
The WE# input is used to control the Data/Command
on the I/O lines during write operations. The I/O lines
are latched on the rising edge of the WE# signal.
Write Protect (WP#)
The WP# input provides protection from inadvertent
program/erase commands. The internal voltage regu-
lator is reset when WP# is low, thereby preventing any
program or erase operations from occurring.
The WP# input should be kept low (V
IL
) during
power-up until V
CC
is above V
CC
-min. During
power-down WP# should be driven low (V
IL
) before
V
CC
is below V
CC
-min.
Spare Area Enable (SE#)
The SE# input controls access to the 16 bytes of spare
area on each page. When SE# is not asserted (high),
the spare area for the selected page is not enabled,
and all input or output data is directed towards the pri-
mary 512 byte storage space. When SE# is asserted
(low), access to the spare area is enabled, and data
can be transferred to or from the 16 bytes of spare
area for the appropriate page as needed. With SE#
asserted (low) information can still be transferred to or
from the 512 byte main Flash page, but when the end
of the page is reached (byte 511) the device will auto-
matically begin transferring information to or from the
spare area.
During the Read Spare Area command sequence
(50h) the SE# input must be asserted (low) during the
command phase (CLE high). In all other cases when
the spare area is to be accessed, the SE# input must
be asserted (low) at least two access cycles prior to
the spare area access. This would require the SE#
input to be low by the time byte address 510 is se-
lected, and SE# must remain low during the entire
period that the spare area is accessed.
Ready/Busy Output (RY/BY#)
The RY/BY# output indicates the operation status of the
device. When RY/BY# is high, the device is ready to
accept the next operation. When RY/BY# is low, an internal
program, erase, or random read operation is in progress.
RY/BY# is an open drain output pin which allows multi-
ple RY/BY# pins to be wire-ORed together. The
RY/BY# output pin requires an external pull-up resistor
to V
CC
(or V
CCQ
) for proper operation.
Device Power Supply (V
CC
)
The minimum V
CC
operating voltage for the
Am30LV0064D is 2.7 volts. The device has an operat-
ing voltage range from 2.7 volts to 3.6 volts.
Output Buffer Power Supply (V
CCQ
)
The output voltage generated on the device is deter-
mined based on the V
CCQ
power supply input level. A
V
CCQ
of 2.7 to 3.6 volts will allow the device to function
as a 3.0 Volt-only device. A V
CCQ
of 4.5 to 5.5 volts
provides 5 volt I/O tolerance.
All input only signals are 5 volt tolerant by design, in-
dependent of the voltage on V
CCQ
.
Ground (V
SS
)
The V
SS
pins on the device must be grounded.
相關(guān)PDF資料
PDF描述
AM30LV0064DJ40 64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology
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AM30LV0064DJ40F2IT 64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM30LV0064DJ40 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology
AM30LV0064DJ40E21 制造商:Advanced Micro Devices 功能描述:
AM30LV0064DJ40E2I 制造商:Advanced Micro Devices 功能描述:NAND Flash Parallel 3V/3.3V 64Mbit 8M x 8bit 35ns 44-Pin TSOP
AM30LV0064DJ40E2IT 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology
AM30LV0064DJ40F2I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NAND Flash EEPROM
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