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| 型號(hào)： | AM29LV320DB120WME |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 2M X 16 FLASH 3V PROM, 120 ns, PBGA48 |
| 封裝： | 6 X 12 MM, 0.80 MM PITCH, FBGA-48 |
| 文件頁數(shù)： | 53/53頁 |
| 文件大小： | 1008K |
| 代理商： | AM29LV320DB120WME |
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July 30, 2002
Am29LV320D
9
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1.
Am29LV320D Device Bus Operations
Legend: L = Logic Low = V
IL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,
A
IN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A20:A0 in word mode (BYTE# = V
IH), A20:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
3. If WP#/ACC = V
IL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection
depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and
Unprotection”. If WP#/ACC = V
HH, all sectors will be unprotected.
4. D
IN or DOUT as required by command sequence, data polling, or sector protection algorithm.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ0–DQ15 are active and controlled by
CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
IH . The BYTE# pi n de termin es
whether the device outputs array data in words or
bytes.
Operation
CE#
OE#
WE#
RESET#
WP#/ACC
Addresses
DQ0–
DQ7
DQ8–DQ15
BYTE#
= V
IH
BYTE#
= V
IL
Read
L
H
L/H
A
IN
D
OUT
D
OUT
DQ8–DQ14
= High-Z,
DQ15 = A-1
Write
L
H
L
H
A
IN
Accelerated Program
L
H
L
H
V
HH
A
IN
Standby
VCC ±
0.3 V
XX
VCC ±
0.3 V
H
X
High-Z
Output Disable
L
H
L/H
X
High-Z
Reset
X
L
L/H
X
High-Z
Sector Protect (Note 2)
L
H
L
V
ID
L/H
SA, A6 = L,
A1 = H, A0 = L
X
Sector Unprotect
LH
L
V
ID
SA, A6 = H,
A1 = H, A0 = L
X
Temporary Sector
Unprotect
XX
X
V
ID
A
IN
High-Z
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