參數(shù)資料
型號(hào)： AM29LV320DB120WME
廠商： SPANSION LLC
元件分類(lèi)： PROM
英文描述： 2M X 16 FLASH 3V PROM, 120 ns, PBGA48
封裝： 6 X 12 MM, 0.80 MM PITCH, FBGA-48
文件頁(yè)數(shù)： 19/53頁(yè)
文件大?。?/td> 1008K
代理商： AM29LV320DB120WME
26
Am29LV320D
July 30, 2002
access the SecSi Sector region until the system is-
sues the four-cycle Exit SecSi Sector command se-
quence. The Exit SecSi Sector command sequence
returns the device to normal operation. Table 14
shows the address and data requirements for both
command sequences. See also “SecSi
formation.
Byte/Word Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program com-
mand sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or
timings. The device automatically provides internally
generated program pulses and verifies the pro-
grammed cell margin. Table 14 shows the address
and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete,
the device then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. Refer to the Write Operation
Status section for information on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once the device has returned to the read
mode, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a
“0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes or words to the device faster than using
the standard program command sequence. The un-
lock bypass command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle containing the unlock bypass command,
20h. The device then enters the unlock bypass mode.
A two-cycle unlock bypass program command se-
quence is all that is required to program in this mode.
The first cycle in this sequence contains the unlock by-
pass program command, A0h; the second cycle con-
tains the program address and data. Additional data is
programmed in the same manner. This mode dis-
penses with the initial two unlock cycles required in the
standard program command sequence, resulting in
faster total programming time. Table 14 shows the re-
quirements for the command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h. The second cycle need only contain the data 00h.
The device then returns to the read mode.
The device offers accelerated program operations
through the WP#/ACC pin. When the system asserts
V
HH on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that
the WP#/ACC pin must not be at V
HH any operation
other than accelerated programming, or device dam-
age may result. In addition, the WP#/ACC pin must not
be left floating or unconnected; inconsistent behavior
of the device may result.
Figure 4 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 18 for timing diagrams.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM29LV320DB120WMI 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 32M-Bit 4M x 8/2M x 16 120ns 48-Pin FBGA
AM29LV320DB90EC 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 32M-Bit 4M x 8/2M x 16 90ns 48-Pin TSOP
AM29LV320DB90ED 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 32M-Bit 4M x 8/2M x 16 90ns 48-Pin TSOP
AM29LV320DB90EF 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 32M-Bit 4M x 8/2M x 16 90ns 48-Pin TSOP
AM29LV320DB90EI 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 32M-Bit 4M x 8/2M x 16 90ns 48-Pin TSOP
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