參數(shù)資料
型號： AM29BDS643GT7GVAF
廠商： SPANSION LLC
元件分類： PROM
英文描述： 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44
封裝： 9.20 X 8 MM, 0.50 MM PITCH, FBGA-44
文件頁數(shù)： 5/49頁
文件大?。?/td> 833K
代理商： AM29BDS643GT7GVAF
May 8, 2006 25692A2
Am29BDS643G
11
D A TA
SH EE T
Power Saving Function
The Power Save function reduces the amount of
switching on the data output bus by changing the
minimum number of bits possible, thereby reducing
power consumption. This function is active only during
burst mode operations.
The device compares the word previously output to the
system with the new word to be output. If the number of
bits to be switched is 0–8 (less than half the bus width),
the device simply outputs the new word on the data
bus. If, however, the number of bits that must be
switched is 9 or higher, the data is inverted before being
output on the data bus. This effectively limits the
maximum number of bits that are switched for any
given read cycle to eight. The device indicates to the
system whether or not the data is inverted via the PS
(power saving) output. If the word on the data bus is not
inverted, PS = VIL; if the word on the data bus is
inverted, PS = VIH.
During initial power up the PS function is disabled. To
enable the PS function, the system must write the
Enable PS command sequence to the flash device (see
the Command Definitions table).
When the PS function is enabled, one additional clock
cycle is inserted during the initial and second access of
a burst sequence. See Figure 20. The RDY output indi-
cates this condition to the system.
The device is also capable of receiving inverted data
during command and write operations. The host
system must indicate to the device via the PS input
whether or not the input data is inverted. PS must be
driven to VIH for inverted data, or to VIL for non-inverted
data.
To disable the PS function, the system must hardware
reset the device (drive the RESET# input low).
Simultaneous Read/Write Operations with
Zero Latency
This device is capable of reading data from one bank
of memory while programming or erasing in one of the
other three banks of memory. An erase operation may
also be suspended to read from or program to another
location within the same bank (except the sector being
erased). Figure 22 shows how read and write cycles
may be initiated for simultaneous operation with zero
latency. Refer to the DC Characteristics table for
read-while-program and read-while-erase current
specifications.
Writing Commands/Command Sequences
The device has inputs/outputs that accept both ad-
dress and data information. To write a command or
command sequence (which includes programming
data to the device and erasing sectors of memory), the
system must drive AVD# and CE# to VIL, and OE# to
VIH when providing an address to the device, and
drive WE# and CE# to VIL, and OE# to VIH. when writ-
ing commands or data.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word, instead of four.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 7 indicates the address
space that each sector occupies. The device address
space is divided into four banks: Banks A and B con-
tain both 8 Kword boot sectors in addition to 32 Kword
sectors, while Banks C and D contain only 32 Kword
sectors. A “bank address” is the address bits required
to uniquely select a bank. Similarly, a “sector address”
is the address bits required to uniquely select a sector.
Refer to the DC Characteristics table for write mode
current specifications. The AC Characteristics section
contains timing specification tables and timing dia-
grams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the VPP input. This function is primarily in-
tended to allow faster manufacturing throughput at the
factory. If the system asserts VID on this input, the de-
vice automatically enters the aforementioned Unlock
Bypass mode and uses the higher voltage on the input
to reduce the time required for program operations.
The system would use a two-cycle program command
sequence as required by the Unlock Bypass mode.
Removing VID from the VPP input returns the device to
normal operation.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Functions and Au-
information.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# inputs are both held at VCC ± 0.2 V.
The device requires standard access time (tCE) for
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