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參數(shù)資料
| 型號： | AM29BDS643GT7GVAF |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44 |
| 封裝： | 9.20 X 8 MM, 0.50 MM PITCH, FBGA-44 |
| 文件頁數(shù)： | 40/49頁 |
| 文件大?。?/td> | 833K |
| 代理商： | AM29BDS643GT7GVAF |
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May 8, 2006 25692A2
Am29BDS643G
43
D A TA
SH EE T
AC CHARACTERISTICS
Note: Devices should be programmed with wait states as discussed in the “Programmable Wait State” section on page 10.
Figure 20.
Initial Access with Power Saving (PS) Function and Address Boundary Latency
Note: If tAVDSM > 1 CLK cycle, wait state usage is reduced. Figure shows 40 MHz clock, handshaking enabled. Wait state usage
is 4 clock cycles instead of 5. Note that tAVDSM must be less than 76 s for burst operation to begin.
Figure 21.
Example of Extended Valid Address Reducing Wait State Usage
CLK
AVD#
RDY
PS
Address
High-Z
A/DQ0:
A/DQ15
PS
OE#
D0
D1
D2
PS1
PS2
device is programmable from 2 to 7 total cycles
during initial access (here, programmable wait state
function is set to 04h; 6 cycles total)
PS high if data is inverted,
low if data is not inverted
2 additional
wait states if
address is
at boundary
1 additional
wait state to
indicate PS
is enabled
AVD# low with clock
present enables
burst read mode
Address
A16:A21
boundary
latency
tOE
CLK
AVD#
RDY
High-Z
A/DQ
OE#
CE#
D0
D1
D2
tIACC2
tAVDSM
Addresses
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