參數(shù)資料
型號： AM29BDS640GTD4WSI
廠商： SPANSION LLC
元件分類： DRAM
英文描述： 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
中文描述： 4M X 16 FLASH 1.8V PROM, 14 ns, PBGA80
封裝： 11 X 12 MM, 0.80 MM PITCH, FBGA-80
文件頁數(shù)： 61/65頁
文件大?。?/td> 899K
代理商： AM29BDS640GTD4WSI
October 31, 2002
Am29BDS640G
63
AD V A NCE
INF O R M A T IO N
REVISION SUMMARY
Revision A (February 13, 2002)
Initial release.
Revision A+1 (February 19, 2002)
Automatic Sleep Mode
Clarified description to indicate that sleep mode is acti-
vated when the first CLK edge occurs after tACC.
Figure 20, Asynchronous Program Operation
Timings
Modified to show that CLK is don’t care prior to AVD#
going low, and that AVD# must not be low before CE#
transitions low.
Revision A+2 (February 27, 2002)
Extended don’t care section of CLK to falling edge of
WE#.
Revision A+3 (May 9, 2002)
Shifted address, clock, and data cycle references in
third paragraph up by one.
Corrected data for address 23h.
Added table.
Autoselect Command Sequence
Added bottom boot device IDs to table.
Added bottom boot device IDs to table.
RDY: Ready
Corrected address boundary from 63rd word/3Eh to
64th word/3Fh.
DC Characteristics
Added VIO = VIO min to test conditions for VOL and VOH
in table.
Erase/Program Operations table
Added specifications for parameters tCSW1, tCSW2,
tCHW, tAHC.
Added note to indicate AVD# must toggle during
command sequence unlock cycles. Added tCSW1 to
Added figures, which show different timings between
addresses, CLK, WE#, and AVD#.
Added note to indicate AVD# must toggle during data
reads.
Shifted address, clock, and data cycle counts up by
one.
Revision A + 4 (July 26, 2002)
Table 1, Device Bus Operations
Changed Synchronous Write to rising edge of CLK.
Writing Commands/Command Sequences
Added CLK as part of the asynchronous write opera-
tion system drive.
Added VCC and VIO Power-up and Power-down
Sequencing section.
AC Characteristics
Changed tCHW erase/program time from Min to Max.
Figure 20, Asynchronous Program Operation
Timings
Changed tCSW1 reference to WE# from AVD#.
Figure 21, Alternate Asynchronous Program
Operation Timings
Changed to show CLK low after tCHW time.
Figure 22, Synchronous Program Operation
Timings
Removed tACH.
Changed tAHW to tAVSW and added tCSW2.
Figure 23, Alternate Synchronous Program
Operation Timings
Changed tAVCH to tAVHC.
Removed tACH.
DC Characteristics, CMOS Compatible
Corrected ICCB OE# = VIL to = VIH; switched Typ. and
Max. values.
Revision B (October 31, 2002)
Global
Re na me d Ha nd s h a k in g E n a b l e d to R e d u c e d
Wait-State Handshaking
Renamed non-Handshaking to Standard Handshaking
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