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參數(shù)資料
| 型號： | AFE2124 |
| 英文描述： | Dual HDSL/SDSL ANALOG FRONT END |
| 中文描述： | 雙HDSL / SDSL是模擬前端 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 187K |
| 代理商： | AFE2124 |
9
AFE2124
For the transmit channel, the pulse shape and the power
spectral density scale directly with the clock rate. The power
spectral density shown in Curve 1 and the pulse template
shown in Curve 2 are measured at the output of the trans-
former. The transformer and the RC circuit on the output
provide some smoothing for the output transmission. At
lower bit rates, the amount of smoothing will be less.
rxHYB AND rxLINE INPUT
ANTI-ALIASING FILTERS
An external input antialiasing filter is needed on the hybrid
and line inputs as shown in Figure 6. The –3dB frequency of
the input anti-aliasing filter for the rxLINE and rxHYB
differential inputs should be approximately 1MHz for T1
and E1 symbol rates. Suggested values for the filter are
750
for each of the two input resistors and 100pF for the
capacitor. Together, the two 750
resistors and the 100pF
capacitor result in a 3dB frequency of just over 1MHz. The
750
input resistors will result in minimal voltage divider
loss with the input impedance of the AFE2124.
The anti-aliasing filters will give best performance with 3dB
frequency approximately equal to the bit rate. For example,
a 3dB frequency of 320kHz may be used for a single line bit
rate of 320k bits per second.
FIGURE 6. Basic Connection Diagram for Each Channel of the AFE2124.
REF
P
V
CM
REF
N
DV
DD
DV
DD
AV
DD
1/2
AFE2124
AV
DD
AV
DD
rxbaudCLK
rx48xCLK
Data Out
txbaudCLK
tx48xCLK
Data In
HDSL DSP
GNDA
GNDA
GNDA
txLINE+
txLINE–
rxHYB+
rxHYB–
rxLINE–
rxLINE+
0.01
μ
F
–
–
+
+
Compromise
Hybrid
Input Antialias Filter
fc
2 x Symbol Rate
0.01
μ
F
5V Analog
0.1
μ
F
0.1
μ
F
0.1
μ
F
0.1
μ
F
0.1
μ
F
1 - 10
μ
F
100pF
750
100pF
750
750
13
13
750
5V to 3.3V Digital
1:2 Transformer
Tip
Ring
0.1
μ
F
0.1
μ
F
0.1
μ
F
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AFE2124E | 功能描述:電信線路管理 IC Dual HDSL/SDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE2124E/1K | 功能描述:電信線路管理 IC Dual HDSL/SDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE2124E/1KG4 | 功能描述:電信線路管理 IC Dual HDSL/SDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE2124EG4 | 功能描述:電信線路管理 IC Dual HDSL/SDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE2126 | 制造商:BB 制造商全稱:BB 功能描述:Dual HDSL/SDSL ANALOG FRONT END |
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