- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375272 > AFE2124 Dual HDSL/SDSL ANALOG FRONT END PDF資料下載
參數(shù)資料
| 型號(hào)： | AFE2124 |
| 英文描述： | Dual HDSL/SDSL ANALOG FRONT END |
| 中文描述： | 雙HDSL / SDSL是模擬前端 |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大小： | 187K |
| 代理商： | AFE2124 |
7
AFE2124
Data is transmitted and received in synchronization with the
48x transmit and receive clocks (tx48xCLK and rx48xCLK).
There are 48-bit times in each baud period. Data In is
received in the first 16 bits of each baud period. The
remaining 32-bit periods are not used for Data In. Data Out
is transmitted during the first 16 bits of the baud period. A
second interpolated value is transmitted in subsequent bits of
the baud period.
txbaudCLK:
The transmit data baud rate, generated by the
DSP. It is 392kHz for T1 or 584kHz for E1. It may vary from
32kHz (64kbps) to 584kHz (1.168Mbps).
tx48xCLK:
The transmit pulse former oversampling sam-
pling clock, generated by the DSP. It is 48x the transmit
symbol rate or 28.032MHz for 584kHz symbol rate. This
clock should run continuously.
Data In:
This is a 16-bit output data word sent from the DSP
to the AFE. The sixteen bits include tx symbol information
and other control bits, as described below. The data should
be clocked out of the DSP on the falling edge and should be
valid on the rising edge of the tx48xCLK. The AFE2124
reads Data In on the rising edge of the tx48xCLK. The bits
are defined in Table I. Data In is read by the AFE2124
during the first 16 bits periods of each baud period. Only the
first 8 bits are used in the AFE2124. The second 8 bits are
reserved for use in the future products. The remaining 32
bits periods of the baud period are not used for Data In.
Data In Bits
tx Enable Signal—
This bit controls the tx Symbol defini-
tion bits. If this bit is 0, only a 0 symbol is transmitted
regardless of the state of the tx Symbol definition bits. If this
bit is 1, the tx Symbol definition bits determine the output
symbol.
tx Symbol Definition—
These two bits determine the output
2B1Q symbol transmitted.
FIGURE 4. Receive Timing Diagram.
FIGURE 3. Data In Word.
1
MSB
LSB
2
3
1
1
8
Reserved
tx Boost
Loopback
rx Gain
tx Symbol
tx Enable
Data Out
from AFE2124
rx48xCLK
from DSP
rxbaudCLK
from DSP
MSB
Bit 15
LSB
Bit 0
MSB
Bit 15
LSB
Bit 0
Data 1a
Interdata 8 Bits
Data 1
Data 2
Interdata 8 Bits
MSB
Bit 15
4ns
48
1
14
15
16
17
23
24
25
26
39
40
47
48
1
4ns
4ns
4ns
t
rx1
A
B
Receive Timing Notes: (1) A baud period consists of 48 periods of the tx48xCLK. (2) The falling edge of the rxbaudCLK
can occur anywhere in area A. The rising edge can occur anywhere in area B. However, neither edge of the
rxbaudCLK can occur within 4ns (on either side) of any rising edge of rx48xCLK. (3) For all data bits after the MSB of
Data 1, the AFE2124 transfers Data Out on the falling edge of the rx48xCLK. The time from the falling edge of
rx48xCLK until Data Out is stable is t
rx1
.
(4) The AFE2124 transfers the MSB of Data 1 on the falling edge of rxbaudCLK. If the falling edge of rxbaudCLK is
synchronized with the falling edge of rx48xCLK, all of the Data Out bits will be the same width. In any case, the time
from the falling edge of rxbaudCLK until the MSB of Data 1 is stable is t
rx1
.
min
9ns
t
rx1
max
14ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AFE2124E | Dual HDSL/SDSL ANALOG FRONT END |
| AFE8201 | IF Analog-to-Digital Converter with Digital Downconverter |
| AFE8201PFBR | IF Analog-to-Digital Converter with Digital Downconverter |
| AFE8201PFBT | IF Analog-to-Digital Converter with Digital Downconverter |
| AG-TL500 | CTV 6C 6#20 PIN WALL RECP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AFE2124E | 功能描述:電信線路管理 IC Dual HDSL/SDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE2124E/1K | 功能描述:電信線路管理 IC Dual HDSL/SDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE2124E/1KG4 | 功能描述:電信線路管理 IC Dual HDSL/SDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE2124EG4 | 功能描述:電信線路管理 IC Dual HDSL/SDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE2126 | 制造商:BB 制造商全稱:BB 功能描述:Dual HDSL/SDSL ANALOG FRONT END |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。