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參數(shù)資料
| 型號： | AFE2124 |
| 英文描述： | Dual HDSL/SDSL ANALOG FRONT END |
| 中文描述： | 雙HDSL / SDSL是模擬前端 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大小： | 187K |
| 代理商： | AFE2124 |
10
AFE2124
DISCUSSION OF
SPECIFICATIONS
UNCANCELED ECHO
A key measure of transceiver performance is uncancelled
echo. Uncancelled echo is the summation of all of the errors
in the transmit and receive paths of the AFE2124. It includes
effects of linearity, distortion and noise. Uncancelled echo is
tested in production by Burr-Brown with a circuit that is
similar to the one shown in Figure 7.
The measurement of uncancelled echo is made as follows:
The AFE is connected to an output circuit including a typical
1:2 line transformer. The line is simulated by a 135
resistor. Symbol sequences are generated by the tester and
applied both to the AFE and to the input of an adaptive filter.
The output of the adaptive filter is subtracted from the AFE
output to form the uncanceled echo signal. Once the filter
taps have converged, the RMS value of the uncancelled echo
is calculated. Since there is no far-end signal source or
additive line noise, the uncanceled echo contains only noise
and linearity errors generated in the transmit and receive
sections of the AFE2124.
The data sheet value for uncancelled echo is the ratio of
the rms uncanceled echo (referred to the receiver input
through the receiver gain) to the nominal transmitted signal
(13.5dBm into 135
, or 1.74Vrms). This echo value is
measured under a variety of conditions: with loopback
enabled (line input disconnected); with loopback disabled
under all receiver gain ranges; and with the line shorted (S
1
closed in Figure 7).
POWER DISSIPATION
Approximately 80% of the power dissipation in the AFE2124
is in the analog circuitry, and this component does not
FIGURE 7. Uncancelled Echo Test Diagram.
TYPICAL POWER DISSIPATION
IN THE AFE2124 (per channel)
(mW)
BIT RATE
(symbols/sec)
DV
DD
(V)
584 (E1)
584 (E1)
392 (T1)
392 (T1)
146 (E1/4)
146 (E1/4)
+3.3
+5
+3.3
+5
+3.3
+5
250
300
240
270
230
245
TABLE II. Typical Power Dissipation (per channel).
change with clock frequency. However, the power dissipa-
tion in the digital circuitry does decrease with lower clock
frequency. In addition, the power dissipation in the digital
section is decreased when operating from a smaller supply
voltage, such as 3.3V. (The analog supply, AV
DD
, must
remain in the range 4.75V to 5.25V).
The power dissipation listed in the Specifications Table
applies under these normal operating conditions: 5V analog
power supply; 3.3V digital power supply; standard 13.5dBm
delivered to the line; and a pseudo-random equiprobable
sequence of HDSL output pulses. The power dissipation
specifications includes all power dissipated in the AFE2124;
however, it does not include power dissipated in the exter-
nal load. The external power is 16.5dBm, 13.5dBm to the
line, and 13.5dBm to the impedance matching resistors. The
external load power of 16.5dBm is 45mW. The typical
power dissipation for each half of the AFE2124 under
various conditions is shown in Table II.
The T1 and E1 power measurements in the Specifications
are made with the output circuit shown in Figure 7. This
circuit uses a 1:2 transformer. The power measurements
shown in Table II use an equivalent resistive load instead of
the transformer to eliminate frequency dependent imped-
ances of the transformer.
rxHYB
N
1/2
AFE2124
rxLINE
P
rxLINE
N
rxD13 - rxD0
rxHYB
P
txLINE
N
txLINE
P
txDAT
P
100pF
1.5k
3k
13
13
5.6
1:2
5.6
1.5
100pF
750
Transmit
Data
Uncancelled
Echo
750
135
S
1
A
F
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AFE2124E | 功能描述:電信線路管理 IC Dual HDSL/SDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE2124E/1K | 功能描述:電信線路管理 IC Dual HDSL/SDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE2124E/1KG4 | 功能描述:電信線路管理 IC Dual HDSL/SDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE2124EG4 | 功能描述:電信線路管理 IC Dual HDSL/SDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE2126 | 制造商:BB 制造商全稱:BB 功能描述:Dual HDSL/SDSL ANALOG FRONT END |
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