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參數(shù)資料
| 型號(hào)： | AFE2124 |
| 英文描述： | Dual HDSL/SDSL ANALOG FRONT END |
| 中文描述： | 雙HDSL / SDSL是模擬前端 |
| 文件頁(yè)數(shù)： | 11/11頁(yè) |
| 文件大?。?/td> | 187K |
| 代理商： | AFE2124 |
11
AFE2124
LAYOUT
The analog front end of an HDSL system has two conflicting
requirements. It must accept and deliver moderately high
rate digital signals and it must generate, drive, and convert
precision analog signals. To achieve optimal system perfor-
mance with the AFE2124, both the digital and the analog
sections must be treated carefully in board layout design.
The power supply for the digital section of the AFE2124 can
range from 3.3V to 5V. This supply should be decoupled to
digital ground with ceramic 0.1
μ
F capacitors placed as close
to DGND and DV
DD
as possible. One capacitor should be
placed between pins 7 and 8 and the second capacitor,
between pins 41 and 42. Ideally, both a digital power supply
plane and a digital ground plane should run up to and
underneath the digital pins of the AFE2124 (pins 1 through
6, and pins 43 through 48). However, DV
DD
may be supplied
by a wide printed circuit board (PCB) trace. A digital ground
plane underneath all digital pins is strongly recommended.
The remaining portion of the AFE2124 should be considered
analog. All AGND pins should be connected directly to a
common analog ground plane and all AV
DD
pins should be
connected to an analog 5V power plane. Both of these planes
should have a low impedance path to the power supply. The
analog power supply pins should be decoupled to analog
ground with ceramic 0.1
μ
F capacitors placed as close to the
AFE2124 as possible. One 10
μ
F tantalum capacitor should
also be used with each AFE2124 between the analog supply
and analog ground.
Ideally, all ground planes and traces and all power planes
and traces should return to the power supply connector
before being connected together (if necessary). Each ground
and power pair should be routed over each other, should not
overlap any portion of another pair, and the pairs should be
separated by a distance of at least 0.25 inch (6mm). One
exception is that the digital and analog ground planes should
be connected together underneath the AFE2124 by a small
trace.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AFE2124E | 功能描述:電信線路管理 IC Dual HDSL/SDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE2124E/1K | 功能描述:電信線路管理 IC Dual HDSL/SDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE2124E/1KG4 | 功能描述:電信線路管理 IC Dual HDSL/SDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE2124EG4 | 功能描述:電信線路管理 IC Dual HDSL/SDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE2126 | 制造商:BB 制造商全稱:BB 功能描述:Dual HDSL/SDSL ANALOG FRONT END |
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