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參數(shù)資料
| 型號： | AFE1230E |
| 英文描述： | G.SHDSL ANALOG FRONT-END |
| 中文描述： | 灣SHDSL的模擬前端 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大小： | 313K |
| 代理商： | AFE1230E |
AFE1230
SBWS015A
9
Digital Data Scale
The digital input and output data is coded in Binary Two’s
complement with 16 bits; the scale is shown in Table VIII.
or txBaud symbol clocks move one MCLK period forward
or backward, resulting in 49 or 47 MCLK cycles per rxBaud),
the receive data will be invalid for six symbol periods while
the data settles to the final value.
Loop Back
The AFE1230 includes digital and analog loop-back options,
as shown in Table IX.
Echo Cancellation in the AFE1230
The rxHYB input is designed to be subtracted from the
rxLINE input for first-order echo cancellation. To accom-
plish this, note that the rxLINE input is connected to the
same polarity signal at the transformer (+ to + and – to –),
while the rxHYB input is connected to opposite polarity
through the compromise hybrid (– to + and + to –).
TABLE VI. rx Data Structure.
TABLE VII. rx Data Format.
BIT
DESCRIPTION
BIT STATE
OUTPUT STATE
47-32
31-24
23-8
7-0
rx A/D Converter Word 1
Reserved
rx A/D Converter Word 2
Reserved
XXXX
16-Bit Binary Two's Complement Word from rx A/D Converter (MSB First)
Reserved for Future Use
16-Bit Binary Two's Complement Word from rx A/D Converter (MSB First)
Reserved for Future Use
Set All Bits Always to 0
XXXX
Set All Bits Always to 0
TABLE VIII. Digital Input/Output Data Scale.
ANALOG INPUT
A/D CONVERTER DATA
MSB
LSB
Positive Full Scale
Mid Scale
Negative Full Scale
0111111111111111
0000000000000000
1000000000000000
TABLE IX. Loopback Table.
LOOPBACK
OPERATION
Loopback = 00
Loopback = 01
Loopback = 10
Loopback = 11
Normal Operation
Digital Loopback: Data In is Shortened to Data Out.
Analog Loopback: The rxLINE inputs are shortened to V
CM
, while the transmit and rxHYB inputs are connected normally.
Analog Loopback: The rxHYB inputs are shortened to V
CM
, while the transmit and rxLINE inputs are connected normally.
16
MSB
8
rx Data Word 2
Spare
Spare
rx Data Word 1
8
16
Sampling Phase
The DSP will determine the sampling phase used for the
AFE1230. In the case of a phase jump (i.e.: when the rxBaud
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AFE1230E/1K | 功能描述:電信線路管理 IC G.SHDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1230E/1KG4 | 功能描述:電信線路管理 IC G.SHDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1230E-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AFE1230E-1/1K | 制造商:Texas Instruments 功能描述: |
| AFE1230EG4 | 功能描述:電信線路管理 IC G.SHDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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