參數(shù)資料
型號(hào)： AFE1230E
英文描述： G.SHDSL ANALOG FRONT-END
中文描述： 灣SHDSL的模擬前端
文件頁數(shù)： 3/15頁
文件大?。?/td> 313K
代理商： AFE1230E
AFE1230
SBWS015A
3
AFE1230E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RECEIVE CHANNEL
Number of Inputs
Input Voltage Range
Common-Mode Voltage
A/D Converter Code
Programmable Gain Range
Gain Absolute Accuracy
Gain Step Accuracy
Settling Time for Gain Change
Output Data Coding
MCLK
System Bit Rate
Symbol Rate
Output Word Rate (OWR)
Filter Cutoff Frequency
(3)
Differential
2
Balanced Differential
(1)
±
3.1
AV
DD
/2
16
V
V
Σ
A/D Converter
3dB Steps
R
IN
= 10k
Bits
dB
%
dB
0
+21
±
20%
3dB Steps, Accuracy Relative to Gain = 1
±
0.5
6
Symbol Periods
Bits
MHz
bps
kHz
kHz
OWR
Binary Two's Complement
Master Clock
16
1.28
80k
26.7
53.4
0.25
40.8
2.55M
850
1700
0.5
Three Bits/Symbol
Two rx Words/Symbol Period
(2)
Programmable 5th-Order LPF,
0.25x and 0.5x OWR
TRANSMIT CHANNEL
D/A Converter Code
Output Line Power
(4)
Σ
D/A Converter
Internal Line Driver, PAR = 3,
Provides 14.5dBm at 135
Line
with 1:3.7 Transformer
Internal Line Buffer, PAR = 4,
Load is External Driver OPA2677
Balanced Differential
16
Bits
dBm
14.5
Output Power
(5)
10
dBm
Output Voltage
Common-Mode Voltage, V
CM
Output Resistance
Input Data Coding
MCLK
System Bit Rate
Input Symbol Rate
Input Word Rate (IWR)
Filter Cutoff Frequency
(6)
±
3.1
AV
DD
/2
0.2
16
V
V
DC to 1MHz
Binary Two's Complement
Master Clock
Three Bits/Symbol
Three Bits/Symbol
Two Words/Symbol Period
5th or 7th LPF, 0.25x, 0.38x, 0.5x IWR
Bits
MHz
bps
kHz
kHz
IWR
1.28
80k
26.7
53.4
0.25
40.8
2.55M
850
1700
0.5
TRASNSCEIVER PERFORMANCE
Uncancelled Echo
(7)
rxGAIN = 12dB
–
80
dB
DIGITAL INTERFACE
Logic Levels:
V
IH
V
IL
V
OH
V
OL
POWER
Analog Power-Supply Voltage
Analog Power-Supply Voltage
Digital Power-Supply Voltage
Digital Power-Supply Voltage
Power Dissipation
(8)
|I
IH
| < 10
μ
A
|I
IL
| < 10
μ
A
I
OH
=
–
20
μ
A
I
OL
= 20
μ
A
DV
DD
–
1
–
0.3
DV
DD
–
0.5
DV
DD
+ 0.3
+0.8
V
V
V
V
+0.4
Specification
Operating Range
Specification
Operating Range
AV
= 5V, DV
DD
= 3.3V,
14.5dBm at 135
Line, E1
AV
DD
= 5V, DV
DD
= 3.3V
5
V
V
V
V
4.75
5.25
3.3
3.15
5.25
750
mW
Power Dissipation
(9)
PSRR
560
60
mW
dB
TEMPERATURE RANGE
Operating
(10)
–
40
+85
°
C
ELECTRICAL CHARACTERISTICS
All specifications are typical at 25
°
C, AV
DD
= +5V, DV
DD
= +3.3V, MCLK = 37.1MHz (E1 rate), unless otherwise noted.
NOTES: (1) With a balanced differential signal, the positive input is 180
°
out-of-phase with the negative input, therefore, the actual voltage swing about the common-
mode voltage on each pin is
±
1.55V to achieve a total input range of
±
3.1V or 6.2Vp-p. (2) The A/D converter oversamples the receive signal and outputs data words
at twice the symbol rate; the A/D converter conversion rate is called the Output Word Rate (OWR). (3) The digital low-pass filter that is part of the A/D converter can
be programmed by the user for a 3dB frequency of 1/2 of the OWR or 1/4 of the OWR. (4) The internal line driver is designed for G.SHDSL. (5) An external driver
(OPA2677) should be used for HDSL2 application. (6) The cutoff frequencies are user programmable. (7) Uncancelled echo is the sum of all noise and distortion
errors for both the transmit and receive channels. (8) For a random sequence of the symbol, using an internal driver providing 14.5dBm power to the line for G.SHDSL.
(9) For a random sequence while driving an external line driver (OPA2677) for HDSL2. (10) Functionality only guaranteed over temperature range.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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AFE1230E/1KG4 功能描述:電信線路管理 IC G.SHDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
AFE1230E-1 制造商:Rochester Electronics LLC 功能描述:- Bulk
AFE1230E-1/1K 制造商:Texas Instruments 功能描述:
AFE1230EG4 功能描述:電信線路管理 IC G.SHDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
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