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參數(shù)資料
| 型號： | AFE1230E |
| 英文描述： | G.SHDSL ANALOG FRONT-END |
| 中文描述： | 灣SHDSL的模擬前端 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大小： | 313K |
| 代理商： | AFE1230E |
AFE1230
SBWS015A
12
LAYOUT
The AFE1230 has two conflicting requirements: it must
accept and deliver high-speed digital signals and it must
generate, drive, and convert precision analog signals. To
achieve optimal system performance with the AFE1230,
both the digital and the analog sections must be treated
carefully in board layout design. The power supply for the
digital section of AFE1230 can range from 3.3V to 5V. This
supply should be decoupled to digital grounds with ceramic
0.1
μ
F capacitors placed as close to the GNDD and DV
DD
pins as possible. DV
DD
may be supplied by a wide-printed
circuit board trace. A digital ground plane underneath all
digital pins is strongly recommended. All GNDA pins should
be connected directly to a common analog ground plane and
all the AV
DD
pins should be connected to an analog 5V
power plane. Both of these planes should have a low imped-
ance path to power supply. The analog power-supply pins
should be decoupled to analog grounds with ceramic 0.1
μ
F
capacitors placed as close to the AFE1230 as possible. One
10
μ
F tantalum capacitor should be used between the analog
supply and analog ground. Ideally, all ground planes and
traces and all power planes and traces should return to the
power connector before being connected together (if neces-
sary). Each ground and power pair should be routed over
each other, and should not overlay any portion of another
pair, and the pairs should be separated by a distance of 0.25
inches (6mm) at least. One exception is that the digital and
analog ground planes should be connected together under-
neath the AFE1230 by a small trace.
FIGURE 10. AFE1230 Line Interface with OPA2677 for HDSL2.
0.47
μ
F
135
1:2.3
22nF
Zi
22nF
R
1
10.9
txLINE+
txLINE
–
rxHYBp
rxHYBm
rxLINE+
rxLINE
–
Overload
Protection
Compromise
Network
OPA2677-a
OPA2677-b
499
499
R
2
10.9
0.1
μ
F
0.1
μ
F
0.1
μ
F
0.1
μ
F
R
453
453
453
2k
2k
0.11
μ
F
1k
1.2nF
1
μ
F
+12V
1
μ
F
10pF
(1)
3.3pF
(1)
10pF
(1)
3.3pF
(1)
49.9
49.9
0.1
μ
F
0.1
μ
F
R
3
10k
R
5
10k
R
4
10k
R
6
10k
AFE1230
17.3Vp-p
NOTE: (1) These components provide low-pass filtering and are optional, since the AFE1230 provides an internal low-pass
filter with 1MHz cutoff frequency on the front end of the receiver, as well as oversampling by the A/D converter.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AFE1230E/1K | 功能描述:電信線路管理 IC G.SHDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1230E/1KG4 | 功能描述:電信線路管理 IC G.SHDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1230E-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AFE1230E-1/1K | 制造商:Texas Instruments 功能描述: |
| AFE1230EG4 | 功能描述:電信線路管理 IC G.SHDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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