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參數(shù)資料
| 型號(hào)： | AFE1230E |
| 英文描述： | G.SHDSL ANALOG FRONT-END |
| 中文描述： | 灣SHDSL的模擬前端 |
| 文件頁(yè)數(shù)： | 4/15頁(yè) |
| 文件大?。?/td> | 313K |
| 代理商： | AFE1230E |
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AFE1230
SBWS015A
4
FIGURE 1. Functional Block Diagram of the AFE1230.
signal is processed by a sinc
5
filter as well as a programmable
IIR filter for droop compensation and additional quantization
noise reduction. The resulting digital signal is sent to the serial
interface for processing by the DSP.
Transmit Filter
The transmit filter consists of two sections, a digital interpo-
lation filter and a programmable SC low-pass filter (SCLPF).
The interpolation filter is an anti-imaging low-pass filter.
The SCLPF serves two important functions. First it is
designed to remove quantization noise from the delta-sigma
D/A converter in the front end of the transmit path. Sec-
ondly, the filter is used to help shape the received digital
signal’s spectral density in conjunction with pre-spectral
shaping within the DSP. Depending on the particular re-
sponse desired, the transmit filter section can be programmed
for three different breakpoints, as shown in Table 1, as well
as two filter order (fifth or seventh) configurations. The 3dB
frequency listed in Table I is in relation to the designed
breakpoint for the SC filter only. However, because the
digital signal is sampled and held for 24 more samples (the
AFE1230 increases the sample rate by 24x in relation to the
input data rate), the actual transmit spectral curves contain a
small amount of droop due to the sinc function performed by
the sample and hold function of the delta-sigma modulator
section of the transmit path. See Figures 2 and 3 for the
overall spectral templates.
APPLICATION INFORMATION
THEORY OF OPERATION
The AFE1230 consists of a transmitter and receiver section, as
shown in Figure 1; the transmitter section consists of a digital
interpolation filter, a 16-bit, delta-sigma D/A converter, a
programmable fifth-order or seventh-order SC low-pass filter,
and a differential output line driver. The receiver section
includes a digitally programmable gain amplifier, a 16-bit,
delta-sigma A/D converter, and a decimation filter. The
AFE1230 receives a 16-bit word plus an 8-bit control byte via
the serial interface to facilitate the D/A conversion and control
functions. The received 16-bit word is up sampled by two
through the digital interpolation filter, then oversampled by
the delta-sigma modulator by a factor of 12x where it is then
processed by the multilevel D/A converter section before being
filtered by the fifth-order or seventh-order Butterworth low-
pass SC filter section.
The subsequent analog signal is sent to the on-chip line driver
where the analog signal can be driven into an appropriate
transformer to provide up to 14.5dBm power into a 135
line
for G.SHDSL. In addition, the on-chip line driver can be used
as an output buffer to generate 17dBm into a 135
line via an
external line driver (such as the OPA2677) for HDSL2. With an
appropriate DSP, the transmitted PSD complies with either the
G.SHDSL standard or, with an OPA2677 used as an external
driver, the HDSL2 standard.
In the receive path, the input amplifier sums the signals from the
line and hybrid paths to perform first-order analog echo cancel-
lation. The resultant signal is then digitized by a fourth-order
cascaded delta-sigma A/D converter with an OSR
(OverSampling Ratio) of 24x. The subsequent oversampled
TABLE I. tx Filter Cutoff Frequency Setting.
tx CUTOFF (txData Bits 29, 28)
RATIO (Corner Frequency)
00
01
10
0.25 MCLK/24
0.38 MCLK/24
0.5 MCLK/24
Σ
16-Bit
A/D Converter
PGA
Input
Amplifier
Patents Pending
AFE1230
Driver/
Buffer
txLINE
txLINE
hybINPUT
hybINPUT
rxINPUT
rxINPUT
OPA2677
tx and rx
Digital
Interface
Registers
Programmable
Digital
LPF
Digital
Interpolation
LPF
Programmable
SC
LPF
Σ
16-Bit
D/A Converter
MCLK
txBaud
txData
rxBaud
rxData
VrRef
External Driver
for HDSL2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AFE1230E/1K | 功能描述:電信線路管理 IC G.SHDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1230E/1KG4 | 功能描述:電信線路管理 IC G.SHDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1230E-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AFE1230E-1/1K | 制造商:Texas Instruments 功能描述: |
| AFE1230EG4 | 功能描述:電信線路管理 IC G.SHDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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