參數(shù)資料
型號: ADV7391BCPZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 103/108頁
文件大?。?/td> 0K
描述: IC VIDEO ENCODER SD/HD 32-LFCSP
產(chǎn)品變化通告: ADV734x, ADV739x Feature Improvement
標(biāo)準(zhǔn)包裝: 5,000
類型: 視頻編碼器
應(yīng)用: 機(jī)頂盒,視頻播放器,顯示器
電壓 - 電源,模擬: 2.6 V ~ 3.46 V
電壓 - 電源,數(shù)字: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ(5x5)
包裝: 帶卷 (TR)
配用: EVAL-ADV7391EBZ-ND - BOARD EVAL FOR ADV7391 ENCODER
ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 94 of 108
Table 71. 10-Bit 525i YCrCb In, CVBS/Y-C Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (16×).
0x01
0x00
SD input mode.
0x80
0x10
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xCB
Pixel data valid. CVBS/Y-C (S-Video) out.
SSAF PrPb filter enabled. Active video
edge control enabled. Pedestal enabled.
0x88
0x10
10-bit input enabled.
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 72. 10-Bit 525i YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (16×).
0x01
0x00
SD input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x80
0x10
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
0x88
0x10
10-bit input enabled.
Table 73. 10-Bit 525i YCrCb In, RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (16×).
0x01
0x00
SD input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x80
0x10
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
0x88
0x10
10-bit input enabled.
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 74. 16-Bit 525i YCrCb In, YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (16×).
0x01
0x00
SD input mode.
0x80
0x10
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
0x88
0x10
16-bit RGB input enabled.
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 75. 16-Bit 525i YCrCb In, RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset
0x00
0x1C
All DACs enabled. PLL enabled (16×).
0x01
0x00
SD input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x80
0x10
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
0x88
0x10
16-bit RGB input enabled.
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 76. 16-Bit 525i RGB In, YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (16×).
0x01
0x00
SD input mode.
0x80
0x10
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
0x87
0x80
RGB input enabled.
0x88
0x10
16-bit RGB input enabled.
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
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