參數(shù)資料
型號： ADV7189BKSTZ10F
廠商： Analog Devices, Inc.
英文描述： Multiformat SDTV Video Decoder
中文描述： 標清多格式視頻解碼器
文件頁數(shù)： 67/104頁
文件大小： 805K
代理商： ADV7189BKSTZ10F
ADV7189B
Register Name
SD Offset Cb
SD Offset Cr
SD Saturation
Cb
SD Saturation
Cr
NTSC V Bit
Begin
NTSC V Bit End
NTSC F Bit
Toggle
PAL V Bit Begin
PAL V Bit End
PAL F Bit Toggle
Reserved
Drive Strength
Reserved
IF Comp Control
VS Mode
Control
Rev. B | Page 67 of 104
Bit 7
SD_OFF_CB.7
SD_OFF_CR.7
SD_SAT_CB.7
Bit 6
SD_OFF_CB.6
SD_OFF_CR.6
SD_SAT_CB.6
Bit 5
SD_OFF_CB.5
SD_OFF_CR.5
SD_SAT_CB.5
Bit 4
SD_OFF_CB.4
SD_OFF_CR.4
SD_SAT_CB.4
Bit 3
SD_OFF_CB.3
SD_OFF_CR.3
SD_SAT_CB.3
Bit 2
SD_OFF_CB.2
SD_OFF_CR.2
SD_SAT_CB.2
Bit 1
SD_OFF_CB.1
SD_OFF_CR .1
SD_SAT_CB.1
Bit 0
SD_OFF_CB.0
SD_OFF_CR.0
SD_SAT_CB.0
SD_SAT_CR.7
SD_SAT_CR.6
SD_SAT_CR.5
SD_SAT_CR.4
SD_SAT_CR.3
SD_SAT_CR.2
SD_SAT_CR.1
SD_SAT_CR.0
NVBEGDEL O
NVBEGDEL E
NVBEGSIGN
NVBEG.4
NVBEG.3
NVBEG.2
NVBEG.1
NVBEG.0
NVENDDEL O
NFTOGDEL O
NVENDDEL E
NFTOGDEL E
NVENDSIGN
NFTOGSIGN
NVEND.4
NFTOG.4
NVEND.3
NFTOG.3
NVEND.2
NFTOG.2
NVEND.1
NFTOG.1
NVEND.0
NFTOG.0
PVBEGDEL O
PVENDDEL O
PFTOGDEL O
PVBEGDEL E
PVENDDEL E
PFTOGDEL E
PVBEGSIGN
PVENDSIGN
PFTOGSIGN
DR_STR.1
PVBEG.4
PVEND.4
PFTOG.4
DR_STR.0
PVBEG.3
PVEND.3
PFTOG.3
DR_STR_C.1
VS_COAST_
MODE.1
PVBEG.2
PVEND.2
PFTOG.2
DR_STR_C.0
IFFILTSEL.2
VS_COAST_
MODE.0
PVBEG.1
PVEND.1
PFTOG.1
DR_STR_S.1
IFFILTSEL.1
EXTEND_VS_
MIN_FREQ
PVBEG.0
PVEND.0
PFTOG.0
DR_STR_S.0
IFFILTSEL.0
EXTEND_VS_
MAX_FREQ
I
PP
2
The following registers are located in the Common
259H
I2C Register Maps and Register Access sections, Page 2.
Table 84. Interrupt (Page 2) Register Map Details
8F
1
Subaddress
Register Name
Value
rw
Dec
Hex
7
Interrupt Config 0
0001
x000
R_SEL.1
Reserved
65
0x41
Interrupt Status 1
r
66
0x42
PP
C REGISTER MAP DETAILS
Reset
6
INTRQ_
DUR_SEL.0
MV_PS_
CS_Q
MV_PS_
CS_CLR
MV_PS_
CS_MSKB
5
MV_INTRQ
_SEL.1
SD_FR_
CHNG_Q
SD_FR_CH
NG_CLR
SD_FR_CH
NG_MSKB
4
MV_INTRQ
_SEL.0
3
2
MPU_STIM
_INTRQ
1
INTRQ_OP
_SEL.1
SD_
UNLOCK_Q
SD_UNLOCK
_CLR
SD_UNLOCK
_MSKB
GEMD_Q
0
INTRQ_OP
_SEL.0
SD_LOCK_
Q
SD_LOCK_
CLR
SD_LOCK_
MSKB
CCAPD_Q
rw
64
0x40
INTRQ_DU
Interrupt Clear 1
x000
0000
x000
0000
w
67
0x43
Interrupt Mask b1
rw
68
0x44
Reserved
Interrupt Status 2
r
69
70
0x45
0x46
MPU_STIM
_INTRQ_Q
MPU_STIM
_INTRQ_
CLR
MPU_
STIM_INTR
Q_MSKB
WSS_CHN
GD_Q
WSS_
CHNGD_
CLR
WSS_
CHNGD_
MSKB
CGMS_
CHNGD_Q
CGMS_
CHNGD_
CLR
CGMS_
CHNGD_
MSKB
SD_H_LOCK
Interrupt Clear 2
0xxx
0000
w
71
0x47
GEMD_CLR
CCAPD_
CLR
Interrupt Mask b2
0xxx
0000
rw
72
0x48
GEMD_
MSKB
CCAPD_
MSKB
Raw Status 3
r
73
0x49
SCM_LOCK
SD_V_LOCK
SD_OP_
50HZ
SD_OP_
CHNG_Q
SD_OP_
CHNG_CLR
Interrupt Status 3
r
74
0x4A
PAL_SW_LK
_CHNG_Q
PAL_SW_L
K_CHNG_
CLR
PAL_SW_
LK_CHNG_
MSKB
SCM_LOCK
_CHNG_Q
SCM_LOCK
_CHNG_
CLR
SCM_LOCK
_CHNG_
MSKB
SD_AD_
CHNG_Q
SD_AD_CH
NG_CLR
SD_H_LOCK
_CHNG_Q
SD_H_
LOCK_
CHNG_CLR
SD_H_
LOCK_
CHNG_MSKB
SD_V_LOCK
_CHNG_Q
SD_V_LOCK
_CHNG_
CLR
SD_V_
LOCK_
CHNG_MSKB
Interrupt Clear 3
xx00
0000
w
75
0x4B
Interrupt Mask b3
xx00
0000
rw
76
0x4C
SD_AD_
CHNG_
MSKB
SD_OP_
CHNG_MSKB
1
To access the interrupt register map, the register access page[1:0] bits in register address 0x0E must be programmed to 01b.
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7189BKSTZ10F2 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder
ADV7189BST 制造商:Analog Devices 功能描述:
ADV7189KST 制造商:Rochester Electronics LLC 功能描述:12BIT NTSC/PAL/SECAMVIDDECOD I.C. - Tape and Reel 制造商:Analog Devices 功能描述:IC VIDEO ENCODER
ADV7189XST 制造商:Analog Devices 功能描述:54MHZ NTSC/PAL ENCODER(DNR+MACROVISON)IC - Bulk
ADV7189XST-X2 制造商:Analog Devices 功能描述:54MHZ NTSC/PAL ENCODER(DNR+MACROVISON)IC - Bulk
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