參數(shù)資料
型號: ADV7180
廠商: Analog Devices, Inc.
英文描述: 10-Bit, 4 x Oversampling SDTV Video Decoder
中文描述: 10位,4個采樣標(biāo)清視頻解碼器
文件頁數(shù): 80/112頁
文件大?。?/td> 1320K
代理商: ADV7180
ADV7180
Table 103. Register Map Descriptions (Normal Operation)
Rev. A | Page 80 of 112
Bits (Shading Indicates Default
State)
6
5
4
Comments
Subaddress
0x00
Register
Input Control
Bit Description
INSEL [3:0]. The INSEL
bits allow the user to
select an input channel
and the input format.
Refer to
Table 9
and
Table 8
for full routing
details.
7
3
0
0
0
0
0
0
0
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
LQFP-64
Composite
Composite
Composite
Composite
Composite
Composite
S-Video
LFCSP-40
Composite
Reserved
Reserved
Composite
Composite
Reserved
S-Video
Notes
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
S-Video
S-Video
YPrPb
YPrPb
Reserved
Reserved
Reserved
Reserved
Reserved
Autodetect PAL B/G/H/I/D,
NTSC (without pedestal),
SECAM
Autodetect PAL B/G/H/I/D,
NTSC M (with pedestal),
SECAM
Autodetect PAL N, NTSC M
(without pedestal), SECAM
Autodetect PAL N, NTSC M
(with pedestal), SECAM
NTSC J
NTSC M
PAL 60
NTSC 4.43
PAL B/G/H/I/D
PAL N (B/G/H/I/D without
pedestal)
PAL M (without pedestal)
PAL M
PAL Combination N
PAL Combination N
(with pedestal)
SECAM
SECAM (with pedestal)
Set to default
Disable vsync processor
Enable vsync processor
Set to default
Standard video input
Betacam input enable
Disable hsync processor
Enable hsync processor
Set to default
Reserved
Reserved
YPrPb
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Mandatory write required
for Y/C (S-video mode)
Reg 0x58 = 0x04; see
Reg 0x58 for bit description
0
0
0
1
0
0
1
0
0
0
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
1
0
1
0
1
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
1
1
0
1
1
1
0
1
0
1
0
0
1
0
0
0
VID_SEL [3:0]. The
VID_SEL bits allow the
user to select the input
video standard.
Reserved.
ENVSPROC.
Reserved.
BETACAM.
ENHSPLL.
0x01
Video Selection
Reserved.
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