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參數(shù)資料
| 型號(hào)： | ADV7180 |
| 廠(chǎng)商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit, 4 x Oversampling SDTV Video Decoder |
| 中文描述： | 10位，4個(gè)采樣標(biāo)清視頻解碼器 |
| 文件頁(yè)數(shù)： | 12/112頁(yè) |
| 文件大?。?/td> | 1320K |
| 代理商： | ADV7180 |
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ADV7180
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
40-LEAD LFCSP
Rev. A | Page 12 of 112
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
DVDDIO
SFL
DGND
DVDDIO
P7
P6
P5
P4
P3
P2
10
23
A
1
22
TEST_0
21
AGND
24
AGND
25
VREFP
26
27
VREFN
28
AG2
29
A
30
A
IN
3
1
L
1
X
1
X
1
D
1
P
1
P
1
P
1
E
2
P
1
D
3
3
3
3
3
3
3
H
4
3
3
LFCSP
TOP VIEW
(Not to Scale)
ADV7180
0
Figure 7. 40-Lead LFCSP Pin Configuration
Table 8. Pin Function Descriptions for the ADV7180 LFCSP-40
Pin No.
Mnemonic
3, 15, 35, 40
DGND
21, 24, 28
AGND
1, 4
DVDDIO
14, 36
DVDD
27
AVDD
20
PVDD
23, 29, 30
A
IN
1 to A
IN
3
5 to 10, 16, 17
P7 to P2, P1, P0
39
HS
38
INTRQ
Type
G
G
P
P
P
P
I
O
O
O
Function
Ground for Digital Supply.
Ground for Analog Supply.
Digital I/O Supply Voltage (3.3 V).
Digital Supply Voltage (1.8 V).
Analog Supply Voltage (1.8 V).
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
Video Pixel Output Port.
Horizontal Synchronization Output Signal.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video (see Table 104).
Vertical Synchronization Output Signal/Field Synchronization Output Signal.
I
2
C Port Serial Data Input/Output Pin.
I
2
C Port Serial Clock Input. Maximum clock rate of 400 kHz.
Selects the I
2
C Address for the ADV7180. For ALSB set to Logic 0, the address selected for a
write is 0xTBC; for ALSB set to logic high, the address selected is 0xTBC.
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7180 circuitry.
Line-Locked Output Clock for the Output Pixel Data. Nominally 27 MHz, but varies up or
down according to video line length.
Input Pin for the 28.6363 MHz Crystal. Can be overdriven by an external 1.8 V, 28.6363 MHz
clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
This pin should be connected to the 28.6363 MHz crystal, or not connected if an external
1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the
crystal must be a fundamental crystal.
A logic low on this pin places the ADV7180 into power-down mode.
The recommended external loop filter must be connected to this ELPF pin, as shown in
Figure 53.
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
the subcarrier frequency when this decoder is connected to any Analog Devices digital video
encoder.
Internal Voltage Reference Output. See Figure 53 for recommended output circuitry.
Internal Voltage Reference Output. See Figure 53 for recommended output circuitry.
This pin must be tied to DGND.
37
33
34
32
VS/FIELD
SDATA
SCLK
ALSB
O
I/O
I
I
31
RESET
I
11
LLC
O
13
XTAL
I
12
XTAL1
O
18
19
PWRDWN
ELPF
I
I
2
SFL
O
26
25
22
VREFN
VREFP
TEST_0
O
O
I
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7180BCPZ | 10-Bit, 4 x Oversampling SDTV Video Decoder |
| ADV7180BSTZ | 10-Bit, 4 x Oversampling SDTV Video Decoder |
| ADV7181 | Multiformat SDTV Video Decoder |
| ADV7181B | Multiformat SDTV Video Decoder |
| ADV7181BBCPZ | Multiformat SDTV Video Decoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7180_12 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:10-Bit, 4?? Oversampling SDTV Video Decoder |
| ADV7180BCP32Z | 制造商:Analog Devices 功能描述:10-BIT, 4? OVERSAMPLING SDTV VIDEO DECODER - Trays |
| ADV7180BCP32Z-RL | 制造商:Analog Devices 功能描述:IC |
| ADV7180BCPZ | 功能描述:IC VIDEO DECODER SDTV 40-LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 線(xiàn)性 - 視頻處理 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:電平移位器 應(yīng)用:LCD 電視機(jī)/監(jiān)控器 安裝類(lèi)型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:28-WQFN（4x4）裸露焊盤(pán) 包裝:帶卷 (TR) 其它名稱(chēng):296-32523-2TPS65198RUYT-ND |
| ADV7180BCPZ | 制造商:Analog Devices 功能描述:IC VIDEO DECODER 10BIT 57.27MSPS LFCSP40 |
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