參數(shù)資料
型號(hào)： ADV7129KS
廠商： ANALOG DEVICES INC
元件分類： 顯示控制器
英文描述： 192-Bit, 360 MHz True-Color Video DAC with Onboard PLL
中文描述： 2000 X 2000 PIXELS PALETTE-DAC DSPL CTLR, PQFP304
封裝： PLASTIC, QFP-304
文件頁(yè)數(shù)： 9/20頁(yè)
文件大?。?/td> 389K
代理商： ADV7129KS
ADV7129
–9–
REV. 0
Mnemonic
Function
IOR, IOG, IOB
Red, Green & Blue Current Outputs (High Impedance Current Sources). These RGB video outputs are
specified to directly drive RS-343A and RS-170 video levels into doubly terminated 50
or 75
loads.
Differential Red, Green & Blue Current Outputs (High Impedance Current Sources). These RGB video
outputs are specified to directly drive RS-343A and RS-170 video levels into doubly terminated 50
or
75
loads. If the complementary outputs are not required, then these outputs should be tied to GND.
Red Compensation pin. This pin should be bypassed to V
AA
with 0.01
μ
F capacitor.
Green Compensation pin. This pin should be bypassed to V
AA
with 0.01
μ
F capacitor.
Blue Compensation pin. This pin should be bypassed to V
AA
with 0.01
μ
F capacitor.
DAC Output Full-Scale Adjust Control (Analog Input): A resistor from this pin to ground sets the current
in the DACs. The current in the DACs is set according to the equations:
I
OUT
= 12,950
×
V
REF
/
R
SET
(
SYNC
not encoded on the DAC Outpu
t)
I
OUT
= 18,137
×
V
REF
/
R
SET
(
SYNC
encoded on the DAC Outpu
t)
To generate RS 343-A video levels on the DAC outputs, a resistor value of 280
is recommended for
doubly terminated 50
lines. Any combination of R
SET
value, DAC termination resistor and programming
of
SYNC
and pedestal are possible provided that the maximum DAC current and the DAC output compli-
ance specifications are adhered to.
For example, in a doubly terminated 50
system with no
SYNC
or pedestal encoded on the DAC outputs,
an R
SET
value of 280
gives a DAC full-scale output of 52.8 mA, i.e., a white-to-black value of 1.4 V.
This example would give a 6 dB reduction in noise and feedthrough on the DAC outputs (compared to a
0.7 V full-scale value), but may require a 0.5X splitter at the monitor.
IOR
,
IOG
,
IOB
R
COMP
G
COMP
B
COMP
R
RSET,
R
GSET,
R
BSET
R
BIAS
G
BIAS
B
BIAS
SENSE
/SYNCOUT
Red Bias node. This node should be decoupled to V
AA
with a 0.01
μ
F capacitor.
Green Bias node. This node should be decoupled to V
AA
with a 0.01
μ
F capacitor.
Blue Bias node. This node should be decoupled to V
AA
with a 0.01
μ
F capacitor.
Comparator Sense Output (TTL Compatible Output). This output will be logic “1” if one or more of the
analog outputs exceeds the internal voltage of the SENSE comparator circuit. It can be used to determine
the absence of a CRT monitor. The value of the SENSE Output corresponds to the current pixel at the out-
puts. The output can drive one CMOS load. This pin can alternately be programmed to be a TTL sync
output which is a delayed version of
CSYNC
.
Voltage Reference (Analog Input/Output): This should always have a 0.1
μ
F decoupling capacitor attached
between V
REF
and V
AA
. If nothing else is connected then the DACs are driven by the internal voltage refer-
ence. If it is required to use a more accurate reference, then this pin acts as an overdrive input. An external
1.235 V voltage reference such as the AD1580 or equivalent is recommended to drive this input. (Note: It is
not recommended to use a resistor network to generate the voltage reference.)
Power Supply (+5 V
±
5%). The part contains multiple power supply pins, all should be connected together
to one common +5 V filtered analog power supply.
Analog Ground. The part contains multiple ground pins, all should be connected together to the system’s
ground plane.
V
REF
V
AA
GND
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