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參數(shù)資料
| 型號(hào)： | ADV7129KS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | 192-Bit, 360 MHz True-Color Video DAC with Onboard PLL |
| 中文描述： | 2000 X 2000 PIXELS PALETTE-DAC DSPL CTLR, PQFP304 |
| 封裝： | PLASTIC, QFP-304 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 389K |
| 代理商： | ADV7129KS |
ADV7129
–13–
REV. 0
DIGITAL-TO-ANALOG CONVERTERS (DACS)
AND VIDEO OUTPUTS
The ADV7129 contains three high speed video DACs. The
DAC outputs are represented as the three primary analog color
signals IOR (red video), IOG (green video) and IOB (blue
video).
DACs and Analog Outputs
The part contains three matched 8-bit digital-to-analog converters.
The DACs are designed using an advanced, high speed, seg-
mented architecture. The bit currents corresponding to each
digital input are routed to either IOR, IOG, IOB (bit = “1”) or
IOR
,
IOG
,
IOB
(bit = “0”). Normally
IOR
,
IOG
, &
IOB
are
connected to GND.
Z
O
= 50
(CABLE)
Z
L
= 50
(MONITOR)
IOR, IOG, IOB
DACs
Z
S
= 50
(SOURCE TERMINATION)
Figure 10. DAC Output Termination (Doubly Terminated
50
Load)
The analog video outputs are high impedance current sources.
Each of the these three RGB current outputs are specified to di-
rectly drive a 25
load (doubly-terminated 50
).
Reference Input and R
SET
An external 1.235 V voltage reference is preferred to set up the
analog outputs of the ADV7129. The reference voltage is con-
nected to the V
REF
input. In the absence of an external refer-
ence, the on-chip voltage reference is internally connected to
the V
REF
pin. The internal reference will set up the DAC cur-
rents, although with slightly less accuracy.
A resistor R
SET
is connected between the R
SET
(R
RSET
, R
GSET
,
R
BSET
) input of the part and ground. An R
SET
value of 280
corresponds to the generation of two times RS-343A video lev-
els into a doubly-terminated 50
load. Figure 11 illustrates the
resulting video waveform and the Video Output Truth Table il-
lustrates the corresponding control input stimuli. On the
ADV7129
SYNC
can be encoded on any of the analog signals,
however in practice,
SYNC
is generally encoded on either the
IOG output or on all of the video outputs.
Any combination of R
SET
, DAC termination resistors and
programming of
SYNC
and pedestal are possible provided that
the maximum DAC current of 60 mA and the DAC output
compliance specifications are adhered to. The following tables
show the current levels for different values of R
SET
resistors and
R
LOAD
termination.
GRAYSCALE
7.5 IRE
92.5 IRE
40 IRE
SYNC LEVEL
BLANK LEVEL
BLACK LEVEL
WHITE LEVEL
Figure 11. Composite Video Waveform SYNC Decoded;
Pedestal = 7.5 IRE
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