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參數(shù)資料
| 型號： | ADV7129KS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | 192-Bit, 360 MHz True-Color Video DAC with Onboard PLL |
| 中文描述： | 2000 X 2000 PIXELS PALETTE-DAC DSPL CTLR, PQFP304 |
| 封裝： | PLASTIC, QFP-304 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 389K |
| 代理商： | ADV7129KS |
ADV7129
–11–
REV. 0
REGISTER PROGRAMMING
The following section describes each register, including Address
Register and each of the Control Registers in terms of its
configuration.
Address Register (A10–A0)
As illustrated previously, the C1–C0 inputs, in conjunction with
the Address Register specify which control register, or palette
RAM location is accessed by the MPU port. The Address Reg-
ister is 16 bits wide and can be read from as well as written to.
CONTROL REGISTERS
A large bank of registers can be accessed using the Address reg-
ister and C1–C0. Access is made first by writing the Address
Register with the appropriate address to point to the particular
Control Register, and then performing an MPU access to the
Control Register.
ADDRESS REGISTER
(A10–A0)
(A10–A0)
REGISTER ACCESS
4FF–412
411
410
40F
40E
40D
40C
40B
40A
409
408
407
406
405
004
403
402
401
400
000–3FF
RESERVED
COMMAND REGISTER 2
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
BLUE DAC GAIN ERROR REGISTER
GREEN DAC GAIN ERROR REGISTER
RED DAC GAIN ERROR REGISTER
RESERVED
RESERVED
RESERVED
RESERVED
COMMAND REGISTER 1
RESERVED
C1
C0
R/
W
0
0
1
0
0
1
1
0
1
0
0
1
0
1
0
0
0
1
1
1
X
WRITE TO ADDRESS REGISTER (LOWER BYTE)
WRITE TO ADDRESS REGISTER (UPPER BYTE)
WRITE TO REGISTERS
READ FROM ADDRESS REGISTER (LOWER BYTE)
READ FROM ADDRESS REGISTER (UPPER BYTE)
READ FROM REGISTERS
RESERVED
Figure 6. Control Registers
COMMAND REGISTER 1 (CR1)
(Address Register (A10–A0) = 400H)
This register contains a number of control bits as shown in the
diagram. CR1 is an 8-bit wide register.
Figure 7 shows the various operations under the control of CR1.
This register can be read from as well as written to. Bit CR16 is
reserved and should be set to logic “1.”
COMMAND REGISTER 1-BIT DESCRIPTION
BLANK
Control on Inverted Outputs (CR10):
This bit specifies whether the video
BLANK
is to be decoded
onto the inverted analog outputs or ignored.
SYNC
Control on Inverted Outputs (CR11)
This bit specifies whether the video
SYNC
is to be decoded
onto the inverted analog outputs or ignored.
SYNC
Recognition on Blue (CR12)
This bit specifies whether the video
SYNC
input is to be de-
coded onto the IOB analog output or ignored.
SYNC
Recognition on Green (CR13)
This bit specifies whether the video
SYNC
input is to be de-
coded onto the IOG analog output or ignored.
SYNC
Recognition on Red (CR14)
This bit specifies whether the video
SYNC
input is to be de-
coded onto the IOR analog output or ignored.
Pedestal Enable Control (CR15)
This bit specifies whether a 0 IRE or a 7.5 IRE blanking pedes-
tal is to be generated on the video outputs.
Display Mode Control (CR17)
This bit controls whether the display is interlaced or noninterlaced.
CR17
CR16
CR15
CR14
CR13
CR12
CR11
CR10
CR16 = 0
(RESERVED)
ZERO MUST BE
WRITTEN TO THIS BIT
INTERLACE ENABLE
CR17
0
1
DISABLE
ENABLE
PEDESTAL ENABLE
CONTROL
0
1
0 IRE
7.5 IRE
CR15
SYNC RECOGNITION
CONTROL (IOG)
CR13
0
1
IGNORE
DECODE
SYNC RECOGNITION
CONTROL (IOB)
CR12
0
1
IGNORE
DECODE
SYNC RECOGNITION
CONTROL (IOR)
CR14
0
1
IGNORE
DECODE
PEDESTAL CONTROL
(
IOR
,
IOG
,
IOB
)
0
DISABLE BLANK ON
INVERTED OUTPUTS
DECODE BLANK ON
INVERTED OUTPUTS
1
CR10
SYNC CONTROL
(
IOR
,
IOG
,
IOB
)
0
DISABLE SYNC ON
INVERTED OUTPUTS
DECODE SYNC ON
INVERTED OUTPUTS
1
CR11
Figure 7. Command Register 1
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