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參數(shù)資料
| 型號(hào)： | ADV7129KS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | 192-Bit, 360 MHz True-Color Video DAC with Onboard PLL |
| 中文描述： | 2000 X 2000 PIXELS PALETTE-DAC DSPL CTLR, PQFP304 |
| 封裝： | PLASTIC, QFP-304 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大小： | 389K |
| 代理商： | ADV7129KS |
ADV7129
–3–
REV. 0
TIMING SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Units
CLOCK CONTROL & PIXEL PORT
4
LOADIN Clocking Rate, f
LCLK
LOADIN Cycle Time, t
1
LOADIN Low Time, t
2
LOADIN High Time, t
3
LOADIN to LOADOUT Delay, t
4
Pixel Setup Time, t
5
Pixel Hold Time, t
6
10
16.67
6.67
6.67
45
MHz
ns
ns
ns
ns
ns
ns
5
0
2
1
4
MPU PORT
R/
W
, C0, C1 Setup Time, t
7
R/
W
, C0, C1 Hold Time, t
8
CE
Low Time, t
9
CE
High Time, t
10
CE
Asserted to Data-Bus Driven, t
11
CE
Asserted to Data-Bus Valid, t
12
CE
Negated to Data-Bus Invalid, t
13
CE
Negated to Data-Bus Three Stated, t
14
Write Data (D7–D0) Setup Time, t
15
Write Data (D7–D0) Hold Time, t
16
10
10
25
25
2
2.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
20
1
15
10
10
ANALOG OUTPUTS
5
Analog Output Delay, t
17
Analog Output Rise/Fall Time, t
18
Analog Output Transition Time, t
19
RGB Analog Output Skew, t
SK
Pipeline Delay, t
PD
@ 360 MHz
5
0.8
25
ns
ns
ns
ns
PCLKs
1.5
19
PLL PERFORMANCE
6
Jitter (1
σ)
(LOADIN = 45 MHz)
55
ps rms
NOTES
1
TTL inputs values are 0 V to 3 V with input rise/fall times
≥
3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and out-
puts. Analog output load
≤
10 pF. Databus (D7–D0) loaded as shown in Figure 1. Digital output load for SENSE
≤
30 pF.
2
±
5% for all versions.
3
Temperature range (T
to T
), 0
°
C to +70
°
C.
4
Pixel Port consists of the following inputs: Pixel Inputs: RED [A-H], BLUE [A-H], GREEN [A-H].
5
Output Delay is measured from the 50% rising edge of LOADIN to the 50% point of full-scale transition on the A pixel. t
includes the analog delay due to DACs
and internal gate transitions plus the pipeline stages delay. The output delay for pixels B-H will be the output delay to the A pixel (t
) plus the appropriate number
of clock cycles. Output rise/fall time is measured between the 10% and 90% points of full-scale transition. Settling time is measured from the 50% point of full-scale
transition to the output remaining within 1%. (Settling Time does not include clock and data feedthrough.)
6
Jitter is measured by triggering on the output clock, delayed by 15
μ
s and then measuring the time period from the trigger edge to the next edge of the output clock
after the delay. This measurement is repeated multiple times and the rms value is determined.
Specifications subject to change without notice.
(V
AA2
= +5 V, V
REF
= +1.235 V, R
RSET
, R
GSET,
R
BSET
= 280
V
, R
L
= 25
V
for IOG, IOR, IOB, C
L
= 10 pF.
All specifications T
MIN
to T
MAX3
unless otherwise noted.)
TO OUTPUT PIN
+2.1V
100pF
I
SINK
I
SOURCE
Figure 1. LOADIN vs. Pixel Input Data
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