
ADV7129–SPECIFICATIONS
All Versions
Conditions
1
Min
Typ
Max
Units
STATIC PERFORMANCE
3
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
Gray Scale Error
8
Bits
±
1
±
1
±
5
LSB
LSB
% Gray Scale
Binary Coding
Guaranteed Monotonic
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN
2.0
GND – 0.5
V
AA
+ 0.5
0.8
±
10
V
V
μ
A
pF
V
IN
= 0.4 V or 2.4 V
10
DIGITAL OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
I
OH
= –400
μ
A
I
OL
= 3.2 mA
2.4
V
V
μ
A
pF
0.4
±
10
10
ANALOG OUTPUTS
Gray Scale Current Range
Output Current
White Level Relative to Black
Black Level Relative to Blank
Blank Level, Sync Disabled
LSB Size
DAC to DAC Matching
Output Compliance, V
OC
Output Impedance, R
OUT
Output Capacitance, C
OUT
10
60
mA
50.16
4.1
0
52.80
4.32
5
223
2
55.44
4.54
50
mA
mA
μ
A
μ
A
%
V
k
pF
5
1.4
0
10
20
VOLTAGE REFERENCE
Voltage Reference Range, V
REF
Input Current, I
VREF
V
REF
= 1.234 V for Specified
Performance
1.14
1.235
5
1.30
V
μ
A
POWER REQUIREMENTS
V
I
AA
I
AA4
Power Supply Rejection Ratio
5
160
360
0.12
V
mA
mA
%/%
Analog Current
Digital Current @ 360 MHz
200
400
DYNAMIC PERFORMANCE
Clock and Data Feedthrough
5
Glitch Impulse
DAC to DAC Crosstalk
6
–30
50
–23
dB
pV secs
dB
NOTES
1
±
5%
for all versions.
2
Temperature range (T
MIN
to T
MAX
), 0
°
C to +70
°
C, TJ (Silicon Junction Temperature)
≤
100
o
C.
3
Static performance is measured with the Gain Error Registers set to 00H (disabled).
4
I
AA
is measured with a typical dynamic pattern, satisfying the absolute maximum current spec for the DACs.
5
Clock and Data Feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data
feedthrough. TTL input values are 0 V to 3 V, with input rise/fall times
≥
3 ns, measured at the 10% and 90% points. Timing reference points are at 50% for
inputs and outputs.
6
DAC to DAC crosstalk is measured by holding one DAC high while the other two DACs are making low to high and high to low transitions.
Specifications subject to change without notice.
(V
AA1
= +5 V, V
REF
= +1.235 V, R
RSET
, R
GSET,
R
BSET
= 280
V
, R
L
= 25
V
, C
L
= 10 pF.
All specifications T
MIN
to T
MAX2
unless otherwise noted.)
REV. 0
–2–