參數(shù)資料
型號: ADT7473ARQZ-1REEL7
廠商: ANALOG DEVICES INC
元件分類: 溫度/濕度傳感器
英文描述: DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 2.50Cel, RECTANGULAR, SURFACE MOUNT
封裝: ROHS COMPLIANT, MO-137AB, QSOP-16
文件頁數(shù): 5/72頁
文件大?。?/td> 1494K
代理商: ADT7473ARQZ-1REEL7
ADT7473/ADT7473-1
Rev. C | Page 13 of 72
READ OPERATIONS
The ADT7473/ADT7473-1 uses the following SMBus read
protocols.
Receive Byte
This operation is useful when repeatedly reading a single
register. The register address must have been previously set up.
In this operation, the master device receives a single byte from a
slave device, as follows:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
read bit (high).
3.
The addressed slave device asserts ACK on SDA.
4.
The master receives a data byte.
5.
The master asserts NO ACK on SDA.
6.
The master asserts a stop condition on SDA, and the
transaction ends.
In the ADT7473/ADT7473-1, the receive byte protocol is used
to read a single byte of data from a register whose address has
previously been set by a send byte or write byte operation. This
operation is illustrated in Figure 24.
0
46
86-
021
SLAVE
ADDRESS
DATA
A
R
SA
24
3
15
P
6
Figure 24. Single-Byte Read from a Register
Alert Response Address
Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
The SMBALERT output can be used as either an interrupt
output or an SMBALERT. One or more outputs can be
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the following
events occur:
SMBALERT is pulled low.
The master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known and can
be interrogated in the usual way.
If more than one device’s SMBALERT output is low, the
one with the lowest device address has priority in accor-
dance with normal SMBus arbitration.
Once the ADT7473/ADT7473-1 has responded to the alert
response address, the master must read the status registers, and
the SMBALERT is cleared only if the error condition is gone.
SMBus TIMEOUT
The ADT7473/ADT7473-1 includes an SMBus timeout
feature. If there is no SMBus activity for 35 ms, the ADT7473/
ADT7473-1 assumes the bus is locked and releases the bus.
This prevents the device from locking or holding the SMBus
expecting data. Some SMBus controllers cannot work with the
SMBus timeout feature, so it can be disabled.
Configuration Register 1 (0x40)
Bit 6, TODIS = 0; SMBus timeout enabled (default)
Bit 6, TODIS = 1; SMBus timeout disabled
VOLTAGE MEASUREMENT INPUT
The ADT7473/ADT7473-1 has one external voltage measure-
ment channel and can also measure its own supply voltage, VCC.
Pin 14 can measure VCCP. The VCC supply voltage measurement
is carried out through the VCC pin (Pin 3). The VCCP input can
be used to monitor a chipset supply voltage in computer
systems.
ANALOG-TO-DIGITAL CONVERTER
All analog inputs are multiplexed into the on-chip, successive
approximation, analog-to-digital converter. (ADC) This has a
resolution of 10 bits. The basic input range is 0 V to 2.25 V, but
the input has built-in attenuators to allow measurement of VCCP
without any external components. To allow for the tolerance of
the supply voltage, the ADC produces an output of full scale
(768 decimal or 300 hexadecimal) for the nominal input voltage
and thus has adequate headroom to deal with overvoltages.
INPUT CIRCUITRY
The internal structure for the VCCP analog input is shown
in Figure 25. The input circuit consists of an input protection
diode, an attenuator, plus a capacitor to form a first order
low-pass filter that provides the input immunity to high
frequency noise.
04
68
6-
02
2
VCCP
17.5k
52.5k
35pF
Figure 25. Structure of Analog Inputs
VOLTAGE MEASUREMENT REGISTERS
Register 0x21, VCCP Reading = 0x00 default
Register 0x22, VCC Reading = 0x00 default
VCCP LIMIT REGISTERS
Associated with the VCCP measurement channel is a high and
low limit register. Exceeding the programmed high or low limit
causes the appropriate status bit to be set. Exceeding either limit
can also generate SMBALERT interrupts.
Register 0x46, VCCP Low Limit = 0x00 default
Register 0x47, VCCP High Limit = 0xFF default
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