參數(shù)資料
型號(hào): ADT7473ARQZ-1REEL7
廠商: ANALOG DEVICES INC
元件分類: 溫度/濕度傳感器
英文描述: DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 2.50Cel, RECTANGULAR, SURFACE MOUNT
封裝: ROHS COMPLIANT, MO-137AB, QSOP-16
文件頁數(shù): 24/72頁
文件大小: 1494K
代理商: ADT7473ARQZ-1REEL7
ADT7473/ADT7473-1
Rev. C | Page 30 of 72
Example 2
For a PWM duty cycle of 33%
Value (decimal) = 33/0.39 = 85 (decimal)
Value = 85 (decimal) or 0x54 (hex)
PWM Current Duty Cycle Registers
Register 0x30, PWM1 Duty Cycle = 0x00 (0% default)
Register 0x31, PWM2 Duty Cycle = 0x00 (0% default)
Register 0x32, PWM3 Duty Cycle = 0x00 (0% default)
By reading the PWMx current duty cycle registers, the user can
keep track of the current duty cycle on each PWM output, even
when the fans are running in automatic fan speed control mode
or acoustic enhancement mode. See the Programming the
FAN PRESENCE DETECT
This feature can be used to determine if a 4-wire fan is directly
connected to a PWM output. This feature does not work for
3-wire fans. To detect whether a 4-wire fan is connected directly
to a PWM output, the following steps must be performed in this
order:
1.
Drive the appropriate PWM outputs to 100% duty cycle.
2.
Set Bit 0 of Configuration Register 2 (0x73).
3.
Wait 5 ms.
4.
Program the fans to run at a different speed if necessary.
5.
Read the state of Bits [3:1] of Configuration
Register 2 (0x73). The state of these bits reflects whether a
4-wire fan is directly connected to the PWM output.
As the detection time only takes 5 ms, programming the PWM
outputs to 100% and then back to their normal speed is not
noticeable in most cases.
Description of How Fan Presence Detect Works
Typical 4-wire fans have an internal pull up to 4.75 V ± 10%,
which typically sources 5 mA. While the detection cycle is on,
an internal current sink is turned on, sinking current from the
fan’s internal pull-up. By driving some of the current from the
fan’s internal pull-up (~100 μA), the logic buffer switches to a
defined logic state. If this state is high, a fan is present; if it is
low, no fan is present.
The PWM input voltage should be clamped to 3.3 V. This
ensures the PWM output is not pulled to a voltage higher than
the maximum allowable voltage on that pin (3.6 V).
SLEEP STATES
The ADT7473/ADT7473-1 has been specifically designed to
operate from a 3.3 V STBY supply. In computers that support S3
and S5 states, the core voltage of the processor is lowered in
these states. If using the dynamic TMIN mode, lowering the core
voltage of the processor changes the CPU temperature and the
dynamics of the system under dynamic TMIN control. Likewise,
when monitoring THERM, the THERM timer should be
disabled during these states.
Dynamic TMIN Control Register 1 (0X36)
Bit [1] VCCPLO = 1
When the VCCP voltage drops below the VCCP low limit, the
following occurs:
1.
Status Bit 1 (VCCP) in Status Register 1 is set.
2.
SMBALERT is generated, if enabled.
3.
THERM monitoring is disabled. The THERM timer
should hold its value prior to the S3 or S5 state.
4.
Dynamic TMIN control is disabled. This prevents TMIN from
being adjusted due to an S3 or S5 state.
5.
The ADT7473/ADT7473-1 is prevented from entering the
shutdown state.
Once the core voltage, VCCP, goes above the VCCP low limit,
everything is re-enabled, and the system resumes normal
operation.
XNOR TREE TEST MODE
The ADT7473/ADT7473-1 includes an XNOR tree test mode.
This mode is useful for in-circuit test equipment at board-level
testing. By applying stimulus to the pins included in the XNOR
tree, it is possible to detect opens or shorts on the system board.
Figure 47 shows the signals that are exercised in the XNOR tree
test mode. The XNOR tree test is invoked by setting Bit 0
(XEN) of the XNOR tree test enable register (0x6F).
PWM1/XTO
PWM3
PWM2
TACH4
TACH3
TACH2
TACH1
0
46
86
-0
44
Figure 47. XNOR Tree Test
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