參數(shù)資料
型號: ADT7473ARQZ-1REEL7
廠商: ANALOG DEVICES INC
元件分類: 溫度/濕度傳感器
英文描述: DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 2.50Cel, RECTANGULAR, SURFACE MOUNT
封裝: ROHS COMPLIANT, MO-137AB, QSOP-16
文件頁數(shù): 16/72頁
文件大?。?/td> 1494K
代理商: ADT7473ARQZ-1REEL7
ADT7473/ADT7473-1
Rev. C | Page 23 of 72
below TMIN or if the duty cycle in manual mode is set to 0x00,
then pulling the THERM low externally has no effect. See
Figure 33 for more information.
04
68
6-
0
30
THERM
TMIN
THERM ASSERTED TO LOW AS AN INPUT:
FANS DO NOT GO TO 100% BECAUSE
TEMPERATURE IS BELOW TMIN.
THERM ASSERTED TO LOW AS AN INPUT:
FANS DO NOT GO TO 100% BECAUSE
TEMPERATURE IS ABOVE TMIN AND FANS
ARE ALREADY RUNNING.
Figure 33. Asserting THERM Low as an Input
in Automatic Fan Speed Control Mode
THERM TIMER
The ADT7473/ADT7473-1 has an internal timer to measure
THERM assertion time. For example, the THERM input can be
connected to the PROCHOT output of a Pentium 4 CPU to
measure system performance. The THERM input can also be
connected to the output of a trip point temperature sensor.
The timer is started on the assertion of the ADT7473/
ADT7473-1 THERM input and stopped when THERM is
deasserted. The timer counts THERM times cumulatively; that
is, the timer resumes counting on the next THERM assertion.
The THERM timer continues to accumulate THERM assertion
times until the timer is read (it is cleared on read) or until it
reaches full scale. If the counter reaches full scale, it stops at that
reading until cleared.
The 8-bit THERM timer status register (0x79) is designed so
that Bit 0 is set to 1 on the first THERM assertion. Once the
cumulative THERM assertion time has exceeded 45.52 ms, Bit 1
of the THERM timer is set and Bit 0 becomes the LSB of the
timer with a resolution of 22.76 ms (see Figure 34).
When using the THERM timer, be aware of the following.
After a THERM timer read (0x79):
1.
The contents of the timer are cleared on read.
2.
The F4P bit (Bit 5) of Interrupt Status Register 2 needs to
be cleared (assuming that the THERM timer limit has been
exceeded).
If the THERM timer is read during a THERM assertion, then
the following happens:
1.
The contents of the timer are cleared.
2.
Bit 0 of the THERM timer is set to 1 (because a THERM
assertion is occurring).
3.
The THERM timer increments from 0.
4.
If the THERM timer limit (Register 0x7A) = 0x00, the F4P
bit is set.
THERM
TIMER
(REG. 0x79)
THERM ASSERTED
≤ 22.76ms
765
3210
4
000
0001
0
THERM
TIMER
(REG. 0x79)
THERM ASSERTED
≥ 45.52ms
765
3210
4
000
0010
0
THERM
TIMER
(REG. 0x79)
THERM ASSERTED ≥ 113.8ms
(91.04ms + 22.76ms)
765
3210
4
000
0101
0
THERM
ACCUMULATE THERM LOW
ASSERTION TIMES
THERM
ACCUMULATE THERM LOW
ASSERTION TIMES
0
468
6-
0
31
Figure 34. Understanding the THERM Timer
Generating SMBALERT Interrupts from THERM Timer
Events
The ADT7473/ADT7473-1 can generate an SMBALERT when a
programmable THERM timer limit is exceeded. This allows the
system designer to ignore brief, infrequent THERM assertions,
while capturing longer THERM timer events. Register 0x7A is
the THERM timer limit register. This 8-bit register allows a
limit from 0 sec (first THERM assertion) to 5.825 sec to be set
before an SMBALERT is generated. The THERM timer value is
compared with the contents of the THERM timer limit register.
If the THERM timer value exceeds the THERM timer limit
value, the F4P bit (Bit 5) of Interrupt Status Register 2 is set and
an SMBALERT is generated. The F4P bit (Bit 5) of Interrupt
Mask Register 2 (0x75) masks out the SMBALERT if this bit is
set to 1; however, the F4P bit of Interrupt Status Register 2 still
is set if the THERM timer limit is exceeded.
Figure 35 is a functional block diagram of the THERM timer,
limit, and associated circuitry. Writing a value of 0x00 to the
THERM timer limit register (0x7A) causes an SMBALERT to be
generated on the first THERM assertion. A THERM timer limit
value of 0x01 generates an SMBALERT once cumulative
THERM assertions exceed 45.52 ms.
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