參數(shù)資料
型號(hào)： ADSP-21261SKBCZ150
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： SHARC Embedded Processor
中文描述： 16-BIT, 50 MHz, OTHER DSP, PBGA136
封裝： LEAD FREE, MO-205AE, BGA-136
文件頁(yè)數(shù)： 8/44頁(yè)
文件大?。?/td> 396K
代理商： ADSP-21261SKBCZ150
Rev. 0
|
Page 8 of 44
|
March 2006
ADSP-21261
DMA transfers are used to move data to and from internal
memory. Access to the core is also facilitated through the paral-
lel port register read/write functions. The RD, WR, and ALE
(address latch enable) pins are the control pins for the
parallel port.
Timers
The ADSP-21261 has a total of four timers: a core timer able to
generate periodic software interrupts, and three general-
purpose timers that can generate periodic interrupts and be
independently set to operate in one of three modes:
Pulse waveform generation mode
Pulse width count/capture mode
External event watchdog mode
The core timer can be configured to use FLAG3 as a timer
expired output signal, and each general-purpose timer has one
bidirectional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A sin-
gle control and status register enables or disables all three
general-purpose timers independently.
Program Booting
The internal memory of the ADSP-21261 boots at system
power-up from an 8-bit EPROM via the parallel port, an SPI
master, an SPI slave, or an internal boot. Booting is determined
by the boot configuration (BOOTCFG1–0) pins. Selection of the
boot source is controlled via the SPI as either a master or slave
device, or it can immediately begin executing from ROM.
Phase-Locked Loop
The ADSP-21261 uses an on-chip phase-locked loop (PLL) to
generate the internal clock for the core. On power-up, the
CLKCFG1
–
0 pins are used to select ratios of 16:1, 8:1, and 3:1.
After booting, numerous other ratios can be selected via soft-
ware control. The ratios are made up of software configurable
numerator values from 1 to 32 and software configurable divi-
sor values of 1, 2, 4, 8, and 16.
Power Supplies
The ADSP-21261 has separate power supply connections for the
internal (V
DDINT
), external (V
DDEXT
), and analog (A
VDD
/A
VSS
)
power supplies. The internal and analog supplies must meet the
1.2 V requirement. The external supply must meet the 3.3 V
requirement. All external supply pins must be connected to the
same power supply.
Note that the analog supply pin (A
VDD
) powers the processor’s
internal clock generator PLL. To produce a stable clock, it is rec-
ommended that PCB designs use an external filter circuit for the
A
VDD
pin. Place the filter components as close as possible to the
A
VDD
/A
VSS
pins. For an example circuit, see
Figure 4
. (A recom-
mended ferrite chip is the muRata BLM18AG102SN1D). To
reduce noise coupling, the PCB should use a parallel pair of
power and ground planes for V
DDINT
and GND. Use wide traces
to connect the bypass capacitors to the analog power (A
VDD
) and
ground (A
VSS
) pins. Note that the A
VDD
and A
VSS
pins specified
in
Figure 4
are inputs to the processor and not the analog
ground plane on the board—the A
VSS
pin should connect
directly to digital ground (GND) at the chip.
TARGET BOARD JTAG EMULATOR CONNECTOR
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21261 pro-
cessor to monitor and control the target board processor during
emulation. Analog Devices DSP Tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and proces-
sor stacks. The processor’s JTAG interface ensures that the
emulator will not affect target system loading or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro-
priate emulator hardware user’s guide.
DEVELOPMENT TOOLS
The ADSP-21261 is supported by a complete set of
CROSSCORE
software and hardware development tools,
including Analog Devices emulators and VisualDSP++
development environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-21261.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The ADSP-21261
SHARC DSP has architectural features that improve the
efficiency of compiled C/C++ code.
The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in
Figure 4. Analog Power Filter Circuit
CROSSCORE is a registered trademark of Analog Devices, Inc.
VisualDSP++ is a registered trademark of Analog Devices, Inc.
HI Z FERRITE
BEAD CHIP
LOCATE ALL COMPONENTS
CLOSE TO AVDDAND AVSSPINS
A
VDD
A
VSS
100nF
10nF
1nF
ADSP-21261
VDDINT
相關(guān)PDF資料
PDF描述
ADSP-21261SKSTZ150 SHARC Embedded Processor
ADSP-21267 Preliminary Technical Data
ADSP-21267SKBCZ-X Preliminary Technical Data
ADSP-21267SKSTZ-X Preliminary Technical Data
ADSP-21362 SHARC Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21261SKSTZ150 功能描述:IC DSP 32BIT 150MHZ 144LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-21262 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
ADSP-21262_05 制造商:AD 制造商全稱:Analog Devices 功能描述:Embedded Processor
ADSP-21262KSTZ200 制造商:Analog Devices 功能描述:- Trays
ADSP-21262SBBC-150 功能描述:IC DSP 32BIT 150MHZ 136-CSPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
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