參數(shù)資料
型號(hào)： ADSP-21261SKBCZ150
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： SHARC Embedded Processor
中文描述： 16-BIT, 50 MHz, OTHER DSP, PBGA136
封裝： LEAD FREE, MO-205AE, BGA-136
文件頁數(shù)： 15/44頁
文件大?。?/td> 396K
代理商： ADSP-21261SKBCZ150
ADSP-21261
Rev. 0
|
Page 15 of 44
|
March 2006
ADSP-21261 SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
Parameter
1
1
Specifications subject to change without notice.
2
Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, and TRST.
3
Applies to input pin CLKIN.
4
See
Thermal Characteristics on Page 38
for information on thermal specifications.
5
See Engineer-to-Engineer Note (No. 216) for further information.
Min
Max
Unit
V
DDINT
Internal (Core) Supply Voltage
1.14
1.26
V
A
VDD
Analog (PLL) Supply Voltage
1.14
1.26
V
V
DDEXT
V
IH
External (I/O) Supply Voltage
High Level Input Voltage
2
@ V
DDEXT
= max
Low Level Input Voltage
2
@ V
DDEXT
= min
High Level Input Voltage
3
@ V
DDEXT
= max
Low Level Input Voltage @ V
DDEXT
= min
Ambient Operating Temperature
4,
5
3.13
3.47
V
2.0
V
DDEXT
+ 0.5 V
V
IL
–0.5
+0.8
V
V
IH_CLKIN
V
IL_CLKIN
1.74
V
DDEXT
+ 0.5 V
+1.19
–0.5
V
°
C
T
AMB
0
+70
Parameter
1
Test Conditions
@ V
DDEXT
= min, I
OH
= –1.0 mA
3
@ V
DDEXT
= min, I
OL
= 1.0 mA
3
Min
Max
Unit
V
OH
High Level Output Voltage
2
Low Level Output Voltage
2
High Level Input Current
4, 5
Low Level Input Current
4
Low Level Input Current Pull-Up
5
Three-State Leakage Current
6,
7,
8
Three-State Leakage Current
6
Three-State Leakage Current Pull-Up
7
Supply Current (Internal)
9, 10,
11
Supply Current (Analog)
11
Input Capacitance
12,
13
2.4
V
V
OL
0.4
V
I
IH
@ V
DDEXT
= max, V
IN
= V
DDEXT
max
10
μA
I
IL
@ V
DDEXT
= max, V
IN
= 0 V
10
μA
I
ILPU
@ V
DDEXT
= max, V
IN
= 0 V
200
μA
I
OZH
@ V
DDEXT
= max, V
IN
= V
DDEXT
max
10
μA
I
OZL
@ V
DDEXT
= max, V
IN
= 0 V
10
μA
I
OZLPU
@ V
DDEXT
= max, V
IN
= 0 V
t
CCLK
= 6.67 ns, V
DDINT
= 1.2 V, T
AMB
= +25
°
C
200
μA
I
DD-INTYP
375
mA
AI
DD
A
VDD
= max
10
mA
C
IN
f
IN
= 1 MHz, T
CASE
= 25°C, V
IN
= 1.2 V
4.7
pF
1
Specifications subject to change without notice.
2
Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, and XTAL.
3
See
Output Drive Currents on Page 37
for typical drive current capabilities.
4
Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, and CLKIN.
5
Applies to input pins with 22.5 k
Ω
internal pull-ups: TRST, TMS, and TDI.
6
Applies to three-statable pins: FLAG3–0.
7
Applies to three-statable pins with 22.5 k
Ω
pull-ups: AD15–0, DAI_Px, SPICLK, MISO, and MOSI.
8
Applies to open-drain output pins: EMU, MISO, and MOSI.
9
Typical internal current data reflects nominal operating conditions.
10
See Engineer-to-Engineer Note (No. 216) for further information.
11
Characterized, but not tested.
12
Applies to all signal pins.
13
Guaranteed, but not tested.
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