參數(shù)資料
型號： ADSP-21161NYCAZ110
廠商： Analog Devices Inc
文件頁數(shù)： 15/60頁
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 32BIT 225BGA
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： 主機(jī)接口，連接端口，串行端口
時鐘速率： 110MHz
非易失內(nèi)存： 外部
芯片上RAM： 128kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.80V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 225-BGA，CSPBGA
供應(yīng)商設(shè)備封裝： 225-CSPBGA（17x17）
包裝： 托盤
Rev. C
|
Page 22 of 60
|
January 2013
Power-Up Sequencing — Silicon Revision 1.2 and Greater
The timing requirements for DSP startup are given in Table 10.
During the power-up sequence of the DSP, differences in the
ramp-up rates and activation time between the two supplies can
cause current to flow in the I/O ESD protection circuitry. To
prevent damage to the ESD diode protection circuitry, Analog
Devices recommends including a bootstrap Schottky diode.
The bootstrap Schottky diode is connected between the 1.8 V
and 3.3 V power supplies as shown in Figure 9. It protects the
ADSP-21161N from partially powering the 3.3 V supply.
Including a Schottky diode will shorten the delay between
the supply ramps and thus prevent damage to the ESD diode
protection circuitry. With this technique, if the 1.8 V rail rises
ahead of the 3.3 V rail, the Schottky diode pulls the 3.3 V rail
along with the 1.8 V rail.
Figure 9. Dual Voltage Schottky Diode
3.3V I/O
VOLTAGE
REGULATOR
1.8VCORE
VOLTAGE
REGULATOR
VDDEXT
VDDINT
ADSP-21161N
DC INPUT
SOURCE
Table 10. Power-Up Sequencing Silicon Revision 1.2 and Greater (DSP Startup)
Parameter
Min
Max
Unit
Timing Requirements
tRSTVDD
RESET Low Before VDDINT/VDDEXT on
0
ns
tIVDDEVDD
VDDINT on Before VDDEXT
–50
+200
ms
tCLKVDD
CLKIN Valid After VDDINT/VDDEXT Valid
0200
ms
tCLKRST
CLKIN Valid Before RESET Deasserted
10
μs
tPLLRST
PLL Control Setup Before RESET Deasserted
20
μs
tWRST
Subsequent RESET Low Pulsewidth
4tCK
ns
Switching Requirements
tCORERST
DSP core reset deasserted after RESET deasserted
4080tCK
1 Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.8 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.
2 Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to the crystal oscillator manufacturer's data sheet for start-up time.
Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3 Based on CLKIN cycles.
4 Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5 The 4080 cycle count depends on tSRST specification in Table 12. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in
4081 cycles maximum.
Figure 10. Power-Up Sequencing for Silicon Revision 1.2 and Greater (DSP Startup)
RESET
RSTOUT
CLKDBL
CLK_CFG1-0
CLKIN
tRSTVDD
VDDEXT
VDDINT
tPLLRST
tCLKRST
tCLKVDD
tIVDDEVDD
tCORERST
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