參數(shù)資料
型號： ADS62P43IRGCTG4
廠商： Texas Instruments
文件頁數(shù)： 78/78頁
文件大?。?/td> 0K
描述： IC ADC 14BIT SRL/PAR 80M 64VQFN
產(chǎn)品培訓(xùn)模塊： Data Converter Basics
標(biāo)準(zhǔn)包裝： 250
位數(shù)： 14
采樣率（每秒）： 80M
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-VQFN 裸露焊盤（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個差分，單極
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
TIMING CHARACTERISTICS
– LVDS AND CMOS MODES
(continued)
Typical values are specified at 25
°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock,
1.5 VPP clock amplitude, CL = 5 pF
O = 3.5 mA, RL = 100
(3), no internal termination, unless otherwise noted.
Min and max values are specified across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.0 V to 3.6 V,
unless otherwise specified.
ADS62P45
ADS62P44
ADS62P43
ADS62P42
FS = 125 MSPS
FS = 105 MSPS
FS = 80 MSPS
FS = 65 MSPS
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
PARALLEL CMOS MODE, DRVDD = 2.5 V to 3.6 V, default output buffer drive strength (7)
Data setup
Data valid(8) to 50% of
tsu
2.0
3.5
2.8
4.3
5.8
5.7
7.2
ns
time(5)
CLKOUT rising edge
50% of CLKOUT
Data hold
th
rising edge to data
2.0
3.5
2.7
4.2
5.7
5.6
7.1
ns
time(5)
becoming invalid(8)
Clock
Input clock rising edge
tPDI
propagation
zero-cross to 50% of
5.8
7.3
8.8
5.8
7.3
8.8
5.8
7.3
8.8
5.8
7.3
8.8
ns
delay
CLKOUT rising edge
Duty cycle of output
Output clock
clock (CLKOUT)
45% 53%
60%
45% 53%
60%
45%
53%
60% 45%
53%
60%
duty cycle
10
≤ Fs ≤ 125 MSPS
Rise time measured
from 20% to 80% of
Data rise
DRVDD
tr
time
Fall time measured
1.0
1.8
2.5
1.0
1.8
2.5
1.0
1.8
2.5
1.0
1.8
2.5
ns
tf
Data fall
from 80% to 20% of
time
DRVDD
1
≤ Fs ≤ 125 MSPS
Rise time measured
from 20% to 80% of
Output clock
DRVDD
tCLKRISE
rise time
Fall time measured
1.0
1.8
2.5
1.0
1.8
2.5
1.0
1.8
2.5
1.0
1.8
2.5
ns
tCLKFALL
Output clock
from 80% to 20% of
fall time
DRVDD
1
≤ Fs ≤ 125 MSPS
PARALLEL CMOS INTERFACE, DRVDD = 1.8V, maximum buffer drive strength(9)
Input clock rising edge
tSTART
Start time
to data getting valid
8.5
7.5
5.5
3.6
ns
(10) (11)
Width of valid data
tDV
3.3
6.0
5.0
7.5
8.0
10.5
13.5
ns
window
PARALLEL CMOS INTERFACE, DRVDD = 1.8V, MULTIPLEXED MODE, maximum buffer drive strength
FS = 65 MSPS
FS = 40 MSPS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
Input clock falling
Start time,
edge to channel A
tSTART_CHA
0.8
2.3
–4.5
–3
ns
channel A
data getting valid(10)
(11)
Data valid,
Width of valid data
tDV_CHA
5.4
6.4
10.3
11.3
ns
channel A
window
Input clock rising edge
Start time,
tSTART_CHB
to channel B data
1.1
2.4
–4.1
–2.5
ns
channel B
getting valid (10) (11)
Data valid,
Width of valid data
tDV_CHB
5
6
9.7
10.7
ns
channel B
window
(7)
For DRVDD
< 2.2 V, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT). See
Parallel CMOS interface in application section.
(8)
Data valid refers to logic high of 2 V (1.7 V) and logic low of 0.8 V (0.7 V) for DRVDD = 3.3 V (2.5 V).
(9)
For DRVDD
< 2.2 V, output clock cannot be used for data capture. A delayed version of the input clock can be used, that gives the
desired setup
& hold times at the receiving chip
(10) Data valid refers to LOGIC HIGH of 1.26 V and LOGIC LOW of 0.54 V for DRVDD = 1.8 V
(11) Measured from zero-crossing of input clock having 50% duty cycle
Copyright
2007–2012, Texas Instruments Incorporated
9
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