參數(shù)資料
型號: ADS62P43IRGCTG4
廠商: Texas Instruments
文件頁數(shù): 20/78頁
文件大小: 0K
描述: IC ADC 14BIT SRL/PAR 80M 64VQFN
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
標(biāo)準(zhǔn)包裝: 250
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-VQFN 裸露焊盤(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)差分,單極
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
D2-D0
<DECIMATION RATE> Decimation filters
000
Decimate by 2 (pre-defined or user coefficients can be used)
001
Decimate by 4 (pre-defined or user coefficients can be used)
011
NO decimation (Pre-defined coefficients are disabled, only custom coefficients are available)
100
Decimate by 8 (Only custom coefficients are available)
D3
<ODD TAP ENABLE>
0
Even taps enabled (24 coefficients)
1
0 Odd taps enabled (23 coefficients)
D4
<FILTER ENABLE>
0
Digital filter bypassed
1
Digital filter enabled
D5
<FILTER COEFF SELECT>
0
Pre-defined coefficients are loaded in the filter
1
User-defined coefficients are loaded in the filter (coefficients have to be loaded in registers
– to - )
D7
<OFFSET Enable>
0
Offset correction disabled
1
Offset correction enabled
Table 19.
A7
–A0
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
1D
0
<DECIMATION FILTER FREQ BANDS>
D1-D0
<DECIMATION FILTER FREQ BAND> Decimation filters
With decimate by 2,
<DECIMATION RATE> = 000:
00
Low pass filter (
–6 dB frequency at Fs/4)
01
High pass filter (
–6 dB frequency at Fs/4)
10, 11
Unused
With decimate by 4,
<DECIMATION RATE> = 001:
00
Low pass filter (-3 dB frequency at Fs/8)
01
Band pass filter (center frequency at 3Fs/16)
10
Band pass filter (center frequency at 5Fs/16)
11
High pass filter (-3 dB frequency at 3Fs/8)
Copyright
2007–2012, Texas Instruments Incorporated
27
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