參數(shù)資料
型號(hào): ADS62P43IRGCTG4
廠商: Texas Instruments
文件頁(yè)數(shù): 39/78頁(yè)
文件大小: 0K
描述: IC ADC 14BIT SRL/PAR 80M 64VQFN
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
標(biāo)準(zhǔn)包裝: 250
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 64-VQFN 裸露焊盤(pán)(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類(lèi)型: 2 個(gè)差分,單極
50
55
60
65
70
75
80
85
90
Input Amplitude dBFS
SFDR
dBc,
dBFS
G068
SNR
dBFS
SFDR (dBc)
SFDR (dBFS)
SNR (dBFS)
30
40
50
60
70
80
90
100
110
60
50
40
30
20
10
0
fIN = 20.1 MHz
69
70
71
72
73
74
75
76
77
SFDR
dBc
SNR
dBFS
Input Clock Amplitude VPP
G069
78
80
82
84
86
88
90
92
94
0.0
0.5
1.0
1.5
2.0
2.5
3.0
SNR
SFDR
fIN = 20.1 MHz
SNR
dBFS
70
71
72
73
74
75
76
77
78
79
Input Clock Duty Cycle %
SFDR
dBc
G070
SNR
SFDR
fIN = 20.1 MHz
82
84
86
88
90
92
94
96
98
100
25
30
35
40
45
50
55
60
65
70
75
Output Code
0
5
10
15
20
25
30
35
40
8175 8176 8177 8178 8179 8180 8181 8182 8183
Occurence
%
G071
RMS = 1.025 LSB
SNR
dBFS
70
72
74
76
78
80
VVCM VCM Voltage V
SFDR
dBc
G072
85
87
89
91
93
95
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
fIN = 20.1 MHz
External Reference Mode
SNR
SFDR
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
TYPICAL CHARACTERISTICS - ADS62P42 (FS= 65 MSPS) (continued)
All plots are at 25
°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle,
–1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
PERFORMANCE vs INPUT AMPLITUDE
PERFORMANCE vs CLOCK AMPLITUDE
Figure 72.
Figure 73.
OUTPUT NOISE HISTOGRAM WITH
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
INPUTS TIED TO COMMON-MODE
Figure 74.
Figure 75.
PERFORMANCE IN EXTERNAL REFERENCE MODE
Figure 76.
44
Copyright
2007–2012, Texas Instruments Incorporated
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