CLK
參數(shù)資料
型號: ADS1259IPW
廠商: Texas Instruments
文件頁數(shù): 5/48頁
文件大小: 0K
描述: IC ADC 24BIT 14KSPS LN 20TSSOP
產(chǎn)品培訓(xùn)模塊: Industrial Automation Overview
標準包裝: 70
位數(shù): 24
采樣率(每秒): 14k
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
輸入數(shù)目和類型: 2 個單端,單極;2 個單端,雙極;1 個差分,單極;1 個差分,雙極
其它名稱: 296-27184-5
2nd-Order
2nd-Stage
DS
2nd-Order
1st-Stage
DS
AnalogInput(V )
IN
4th-OrderModulator
ToDigitalFilter
f
=f
MOD
CLK/8
ln
FSR
RMSNoise
ln(2)
ENOB=
SBAS424D
– JUNE 2009 – REVISED AUGUST 2011
NOISE PERFORMANCE
MODULATOR
The ADS1259 offers excellent noise performance that
The
high-performance
modulator
is
an
can be optimized by adjusting the data rate and by
inherently-stable, fourth-order,
ΔΣ, 2 + 2 pipelined
selection of the digital filter mode. As the averaging is
structure, as shown in Figure 33. It shifts the
increased by reducing the data rate, the noise drops
quantization noise to a higher frequency (out of the
correspondingly.
Additionally,
because
the
sinc2
passband) where digital filtering can easily remove it.
digital filter provides more filtering than the sinc1
digital filter, sinc2 provides lower noise conversions.
Table 1 shows the noise as a function of data rate
and filter mode.
Table 1 expresses typical noise data in several ways:
RMS noise, effective number of bits (ENOB), and
noise-free bits. ENOB is calculated from Equation 1:
Figure 33. Fourth-Order Modulator
Where:
FSR = 2VREF
(1)
The modulator first stage converts the analog input
voltage into a pulse-code modulated (PCM) stream.
The calculation of noise-free bits uses the same
When the level of differential analog input (AINP
formula as Equation 1, except that the peak-to-peak
AINN) is near the level of the reference voltage
noise value is used instead of RMS noise.
(VREFP
– VREFN), the 1s density of the PCM data
stream is at its highest. When the level of the
ADC
differential analog input is near zero, the PCM 0s and
1s densities are nearly equal. At the two extremes of
The analog-to-digital converter (ADC) section of the
the analog input levels (+FS and
–FS), the 1s density
ADS1259 is composed of two blocks: a high accuracy
of the PCM streams are approximately +90% and
modulator and a programmable digital filter.
+10%, respectively.
The modulator second stage produces a 1s density
data stream designed to cancel the quantization
noise of the first stage. The data streams of the two
stages are then combined in the digital filter stage.
Table 1. Typical Noise Data vs Data Rate and Digital Filter(1)
SINC1 DIGITAL FILTER
SINC2 DIGITAL FILTER
DATA
RATE
SAMPLE
NOISE
ENOB
NOISE-
NOISE
ENOB
NOISE-
(SPS)
SIZE(2)
(
μVRMS)
(
μVPP)
(RMS)
FREE BITS
(
μVRMS)
(
μVPP)
(RMS)
FREE BITS
10
128
0.5
1.8
23.3
21.4
0.45
1.6
23.4
21.6
16.6
256
0.55
2.4
23.1
21.0
0.5
2
23.3
21.3
50
512
0.65
3.5
22.9
20.4
0.6
3
23.0
20.7
60
512
0.7
4
22.8
20.3
0.65
3.5
22.9
20.4
400
4096
1.4
9.5
21.8
19.0
1.2
8.3
22.0
19.2
1200
8192
2.3
17
21.1
18.2
2
14
21.3
18.4
3600
8192
3.9
32
20.3
17.3
3.4
27
20.5
17.5
14400
8192
6.2
50
19.6
16.6
(3)
(1)
Noise data taken with shorted analog inputs and internal 2.5V reference using the circuit of Figure 64.
(2)
Data sample sizes used for analysis.
(3)
Same as sinc1 mode.
Copyright
2009–2011, Texas Instruments Incorporated
13
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