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參數(shù)資料
| 型號： | ADS1259IPW |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 21/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 14KSPS LN 20TSSOP |
| 產品培訓模塊： | Industrial Automation Overview |
| 標準包裝： | 70 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 14k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 20-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，單極；2 個單端，雙極；1 個差分，單極；1 個差分，雙極 |
| 其它名稱： | 296-27184-5 |
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DataUpdating
DRDY
(1)(2)
Pin
20t
CLK
SBAS424D
– JUNE 2009 – REVISED AUGUST 2011
SERIAL INTERFACE
DATA INPUT (DIN)
The SPI-compatible serial interface consists of four
DIN is the input data pin and is used with SCLK to
signals: CS, SCLK, DIN, and DOUT or three signals,
send data to the ADS1259 (opcode commands and
in which case CS may be tied low. The interface is
register data). The device latches input data on the
used to read conversion data, configure registers,
falling edge of SCLK.
and control the ADS1259 operation.
DATA OUTPUT (DOUT)
SERIAL COMMUNICATION
DOUT is the output data pin and is used with SCLK
The ADS1259 communications occur by clocking
to read conversion and register data from the
commands into the device (on DIN) and reading
ADS1259. In addition to providing data output, in
register and conversion data (on DOUT). The SCLK
RDATAC mode DOUT indicates when data are
input is used to clock the data into and out of the
ready. Data are ready when DOUT transitions low. In
device. CS disables the ADS1259 serial port but
this manner, DOUT functions the same as DRDY
otherwise does not affect the ADC operation. The
(with CS = 0), as shown in Figure 57. When reading
communication
protocol
to
the
ADS1259
is
data, the data are shifted out on the rising edge of
half-duplex. That is, data are transmitted to and from
SCLK. DOUT is in a 3-state condition when CS is
the device one direction at a time.
high.
Communications to and from the ADS1259 occurs on
DATA READY (DRDY)
8-bit boundaries. If an unintentional SCLK transition
should occur (such as from a possible noise spike),
DRDY is an output that indicates when conversion
the ADS1259 serial port may not respond properly.
data are available for reading (falling edge active).
The port can be reset by one of the following ways:
DRDY is asserted on an output pin and also a
register bit. To poll the DRDY register bit, set the stop
1. Take CS high and then low to reset the interface
read data continuous mode and then read the
2. Hold SCLK low for 216 fCLK cycles to reset the
CONFIG2 register. When the DRDY bit is low, data
interface
can be read. The data read operation must complete
3. Take RESET/PWDN low and back high to overall
within 20 fCLK cycles of the next DRDY falling edge.
reset the device
After power-on or after reset, DRDY defaults high.
4. Cycle the power supplies to overall reset the
When reading data in Gate Control mode, DRDY is
device
reset high on the first SCLK rising edge. If data are
not retrieved, DRDY pulses high during the new data
CHIP SELECT (CS)
update time, as shown in Figure 57. Do not retrieve data
during this time as the data are invalid.
The chip select (CS) selects the ADS1259 for SPI
communication. To select the device, pull CS low. CS
In Pulse Control mode, DRDY remains low until a
must remain low for the duration of the serial
new conversion is started. The previous conversion
communication. When CS is taken high, the serial
data may be read 20 tCLK prior to the DRDY falling
interface is reset, input commands are ignored, and
edge.
DOUT
enters
a
high-impedance
state.
If
the
ADS1259 does not share the serial bus with another
device, CS may be tied low. Note that DRDY remains
active when CS is high.
SERIAL CLOCK (SCLK)
The serial clock (SCLK) is a Schmitt-triggered input
(1) DOUT functions in the same manner as the DRDY pin if CS is
used to clock data into and out of the ADS1259. Even
low and in the RDATAC mode.
though the input is relatively noise immune, it is
(2) The DRDY bit functions in the same manner as the DRDY pin
recommended to keep SCLK as clean as possible to
(SDATAC mode only).
prevent glitches from accidentally shifting the data. If
Figure 57. DRDY and DOUT With No Data
SCLK is held low for 216 fCLK periods, the serial
Retrieval
interface resets. After reset the next communication
cycle can be started. The timeout can be used to
recover communication when the serial interface is
interrupted. The SPI timeout is enabled by register bit
SPI. When the serial interface is idle, hold SCLK low.
28
Copyright
2009–2011, Texas Instruments Incorporated
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADS1259IPW | 制造商:Texas Instruments 功能描述:A/D CONVERTER (A-D) IC |
| ADS1259IPWR | 功能描述:模數(shù)轉換器 - ADC Low-Noise 14kSPS 24B ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1259QPWRQ1 | 功能描述:24 Bit Analog to Digital Converter 1 Input 1 Sigma-Delta 20-TSSOP 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態(tài):有效 位數(shù):24 采樣率（每秒）:14k 輸入數(shù):1 輸入類型:差分，單端 數(shù)據(jù)接口:SPI 配置:ADC 無線電 - S/H:ADC:- A/D 轉換器數(shù):1 架構:三角積分 參考類型:外部 電壓 - 電源，模擬:5V 電壓 - 電源，數(shù)字:2.7 V ~ 5.25 V 特性:PGA 工作溫度:-40°C ~ 105°C 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商器件封裝:20-TSSOP 標準包裝:1 |
| ADS-125MC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 12-Bit |
| ADS-126 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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