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參數(shù)資料
型號(hào)： ADS1259IPW
廠商： Texas Instruments
文件頁(yè)數(shù)： 15/48頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT 14KSPS LN 20TSSOP
產(chǎn)品培訓(xùn)模塊： Industrial Automation Overview
標(biāo)準(zhǔn)包裝： 70
位數(shù)： 24
采樣率（每秒）： 14k
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 2 個(gè)單端，單極；2 個(gè)單端，雙極；1 個(gè)差分，單極；1 個(gè)差分，雙極
其它名稱(chēng)： 296-27184-5
SCLK
RESETPWDN
/
t
LOW
t
RHSC
CLK
DVDD
InternalReset
1Vnom
AVDD
AVSS
-
3.5Vnom
2
16
t
CLK
ADS1259Operational
SBAS424D
– JUNE 2009 – REVISED AUGUST 2011
RESET/PWDN
RESET
The RESET/PWDN pin has two functions: device
There are three methods to reset the ADS1259: cycle
power-down and device reset. Momentarily holding
the power supplies, take RESET/PWDN low, or send
the pin low resets the device and holding the pin low
the RESET opcode command.
for 216 fCLK cycles activates the Power-Down mode.
When using the RESET/PWDN pin, take it low to
force a reset. Make sure to follow the minimum pulse
POWER-DOWN MODE
width timing specifications before taking the RESET
pin back high.
In power-down mode, internal circuit blocks are
disabled (including the oscillator, reference, and SPI)
The RESET command takes effect on the eighth
and the device enters a micro-power state. To
falling SCLK edge of the opcode command. On reset,
engage power-down mode, hold the RESET/PWDN
the configuration registers are initialized to the default
pin low for 216 fCLK cycles. Note that the register
states and the conversion cycle restarts. After reset,
contents are not saved because they are reset when
allow eight fCLK cycles before communicating to the
RESET/PWDN goes high.
ADS1259. Note that when using the reset command,
the SPI interface itself may require reset before
Keep the digital inputs at defined VIH or VINL logic
accepting
the
command.
See
the
levels (do not 3-state). To minimize power-supply
Characteristics section for details.
leakage current, disable the external clock. Note that
the
ADS1259
digital
outputs
remain
active
in
power-down. The analog signal inputs may float.
POWER-ON SEQUENCE
To exit power-down, take RESET/PWDN high. Wait
The ADS1259 has three power supplies: AVDD,
216
fCLK
cycles
before
communicating
to
the
AVSS, and DVDD. The supplies can be sequenced in
ADS1259, as shown in Figure 48.
any order but be sure that at any time the analog
inputs do not exceed AVDD or AVSS and the digital
inputs do not exceed DVDD. After the last power
supply
has
crossed
the
respective
power-on
threshold,
216
fCLK cycles are counted before
releasing the internal reset. After the internal reset is
released, the ADS1259 is ready for operation.
Figure 49 shows the power-on sequence of the
ADS1259.
Figure 48. RESET/PWDN Timing
Table 6. Timing Characteristics for Figure 48
SYMBOL
DESCRIPTION
MIN
UNIT
tLOW
Pulse width low for reset
4
tCLK
tLOW
Pulse width low for power-down
216
tCLK
tRHSC
Reset high to SPI communication start
8
tCLK
tRHSC
Exit power-down to SPI communication start
216
tCLK
Figure 49. Power-On Sequence
22
Copyright
2009–2011, Texas Instruments Incorporated
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參數(shù)描述
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ADS-126 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:
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