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參數(shù)資料
| 型號： | ADM1027ARQZ-RL7 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 51/56頁 |
| 文件大小： | 1822K |
| 描述： | IC REMOTE THERMAL CTLR 24QSOP |
| 產(chǎn)品變化通告： | MFG CHG Notification ADI to ON Semi Product Discontinuation Notice 25/Aug/2008 Product Obsolescence 30/Sept/2009 |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | dBCool® |
| 功能： | 風(fēng)扇控制，溫度監(jiān)控器 |
| 傳感器類型： | 內(nèi)部和外部 |
| 感應(yīng)溫度： | 0°C ~ 105°C，外部傳感器 |
| 精確度： | ±1°C |
| 拓撲： | ADC，比較器，風(fēng)扇速度計數(shù)器，多路復(fù)用器，寄存器庫 |
| 輸出類型： | SMBus? |
| 輸出警報： | 無 |
| 輸出風(fēng)扇： | 是 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-QSOP |
| 包裝： | 帶卷 (TR) |
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REV. A
ADM1027
51
Table XXIV. XOR Tree Test Enable
Register Address
R/W
Description
Power-On Default
0x6F
Read/Write
XOR Tree Test Enable Register
0x00
<0>
XEN
If the XEN bit is set to 1, the device enters the XOR tree test mode. Clearing the bit
removes the device from the XOR tree test mode.
<7:1>
Reserved
Unused. Do not write to these bits.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register
will have no effect.
Table XXV. Remote 1 Temperature Offset
Register Address
R/W
Description
Power-On Default
0x70
Read/Write
Remote 1 Temperature Offset
0x00
<7:0>
Read/Write
Allows a twos complement offset value to be automatically added to or subtracted from
the Remote 1 temperature reading. This is to compensate for any inherent system offsets
such as PCB trace resistance. LSB value = 1
o
C.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register
will have no effect.
Table XXVI. Local Temperature Offset
Register Address
R/W
Description
Power-On Default
0x71
Read/Write
Local Temperature Offset
0x00
<7:0>
Read/Write
Allows a twos complement offset value to be automatically added to or subtracted from
the local temperature reading. LSB value = 1
o
C.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register
will have no effect.
Table XXVII. Remote 2 Temperature Offset
Register Address
R/W
Description
Power-On Default
0x72
Read/Write
Remote 2 Temperature Offset
0x00
<7:0>
Read/Write
Allows a twos complement offset value to be automatically added to or subtracted from
the Remote 2 temperature reading. This is to compensate for any inherent system off-
sets such as PCB trace resistance. LSB value = 1
o
C.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register
will have no effect.
Rev. 3 | Page 51 of 56 | www.onsemi.com
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