參數(shù)資料
型號: ADAV803ASTZ
廠商: Analog Devices Inc
文件頁數(shù): 26/60頁
文件大小: 0K
描述: IC CODEC AUDIO R-DVD 3.3V 64LQFP
標(biāo)準(zhǔn)包裝: 1
類型: 音頻編解碼器
數(shù)據(jù)接口: 串行
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
動態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 102 / 101
電壓 - 電源,模擬: 3 V ~ 3.6 V
電壓 - 電源,數(shù)字: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
配用: EVAL-ADAV803EBZ-ND - BOARD EVALUATION FOR ADAV803
ADAV803
Rev. A | Page 32 of 60
REGISTER DESCRIPTIONS
SRC and Clock Control—Address 0000000 (0x00)
Table 17. SRC and Clock Control Register Bit Map
7
6
5
4
3
2
1
0
SRCDIV1
SRCDIV0
CLK2DIV1
CLK2DIV0
CLK1DIV1
CLK1DIV0
MCLKSEL1
MCLKSEL0
Table 18. SRC and Clock Control Register Bit Descriptions
Bit Name
Description
SRCDIV[1:0]
Divides the SRC master clock.
00 = SRC master clock is not divided.
01 = SRC master clock is divided by 1.5.
10 = SRC master clock is divided by 2.
11 = SRC master clock is divided by 3.
CLK2DIV[1:0]
Clock divider for Internal Clock 2 (ICLK2).
00 = Divide by 1.
01 = Divide by 1.5.
10 = Divide by 2.
11 = Divide by 3.
CLK1DIV[1:0]
Clock divider for Internal Clock 1 (ICLK1).
00 = Divide by 1.
01 = Divide by 1.5.
10 = Divide by 2.
11 = Divide by 3.
MCLKSEL[1:0]
Clock selection for the SRC master clock.
00 = Internal Clock 1.
01 = Internal Clock 2.
10 = PLL recovered clock (512 × fS).
11 = PLL recovered clock (256 × fS).
S/PDIF Loopback Control—Address 0000011 (0x03)
Table 19. S/PDIF Loopback Control Register Bit Map
7
6
5
4
3
2
1
0
Reserved
TxMUX
Table 20. S/PDIF Loopback Control Register Bit Descriptions
Bit Name
Description
TxMUX
Selects the source for S/PDIF output (DITOUT).
0 = S/PDIF transmitter, normal mode.
1 = DIRIN, loopback mode.
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