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參數(shù)資料
| 型號： | ADAU1781BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/92頁 |
| 文件大小： | 0K |
| 描述： | IC SIGMADSP CODEC LN 32LFCSP |
| 標準包裝： | 1 |
| 系列： | SigmaDSP® |
| 類型： | 立體聲音頻 |
| 數(shù)據(jù)接口： | I²C，串行，SPI? |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 2 / 2 |
| 三角積分調(diào)變： | 無 |
| S/N 比，標準 ADC / DAC (db)： | 100 / 105（差分），100 / 103（單端） |
| 動態(tài)范圍，標準 ADC / DAC (db)： | 99.2 / 105（差分），99.2 / 103（單端） |
| 電壓 - 電源，模擬： | 1.8 V ~ 3.65 V |
| 電壓 - 電源，數(shù)字： | 1.63 V ~ 3.65 V |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ |
| 包裝： | 托盤 |
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ADAU1781
Rev. B | Page 36 of 92
SPI PORT
By default, the ADAU1781 is in I2C mode, but can be put into SPI
control mode by pulling CLATCH low three times. The SPI port
uses a 4-wire interface, consisting of CLATCH, CCLK, CDATA,
and COUT signals, and is always a slave port. The CLATCH
Chip Address R/
signal
goes low at the beginning of a transaction and high at the end of
a transaction. The CCLK signal latches CDATA on a low-to-high
transition. COUT data is shifted out of the ADAU1781 on the
falling edge of CCLK and should be clocked into a receiving
device, such as a microcontroller, on the CCLK rising edge. The
CDATA signal carries the serial input data, and the COUT signal is
the serial output data. The COUT signal remains three-stated until
a read operation is requested. This allows other SPI-compatible
peripherals to share the same readback line. All SPI transactions
have the same basic format shown in Table 24. A timing diagram
is shown in Figure 4. All data should be written MSB first. The
ADAU1781 can be taken out of SPI mode only by a full reset.
W
The first byte of an SPI transaction includes the 7-bit chip address
and an R/W
Table 23. SPI Address Byte Format
bit. The chip address is always 0x38. The LSB of
this first byte determines whether the SPI transaction is a read
(Logic 1) or a write (Logic 0).
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
0
R/W
Subaddress
The 12-bit subaddress word is decoded into a location in one of
the registers. This subaddress is the location of the appropriate
register. The MSBs of the subaddress are zero-padded to bring the
word to a full 2-byte length.
Data Bytes
The number of data bytes varies according to the register being
accessed. During a burst mode write, an initial subaddress is
written followed by a continuous sequence of data for consecutive
register locations. A sample timing diagram for a single-write
SPI operation to the parameter memory is shown in Figure 43.
A sample timing diagram of a single-read SPI operation is shown in
Figure 44. The COUT pin goes from three-state to being driven at
the beginning of Byte 3. In this example, Byte 0 to Byte 2 contain
the addresses and R/W
SPI Read/Write Clock Frequency (CCLK)
bit, and subsequent bytes carry the data.
The SPI port of the ADAU1781 has asymmetrical read and
write clock frequencies. It is possible to write data into the
device at higher data rates than reading data out of the device.
More detailed information is available in the Digital Timing
Specifications section.
MEMORY AND REGISTER ACCESS
Several conditions must be true to have full access to all memory
and registers via the control port:
The ADAU1781 must have finished its initialization,
including power-on reset, PLL lock, and self-boot.
The core clock must be enabled (Register 16384 (0x4000),
clock control, Bit 0, core clock enable, set to 1).
The memory controller must be powered (Register 16512
(0x4080), Digital Power-Down 0, Bit 6, memory controller,
set to 1).
The SigmaDSP core must be powered (Register 16512
(0x4080), Digital Power-Down 0, Bit 0, SigmaDSP core,
set to 1).
Table 24. Generic Control Word Format
Byte 0
Byte 1
Byte 2
Byte 3
Byte 41
CHIP_ADR[6:0], R/W
SUBADR[15:8]
SUBADR[7:0]
Data
1 Continues to end of data.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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