Residual Phase Noise @ 100.3 MHz (f
參數(shù)資料
型號: AD9959BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 41/44頁
文件大小: 0K
描述: IC DDS QUAD 10BIT DAC 56LFCSP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計資源: Phase Coherent FSK Modulator (CN0186)
標(biāo)準(zhǔn)包裝: 1
分辨率(位): 10 b
主 fclk: 500MHz
調(diào)節(jié)字寬(位): 32 b
電源電壓: 1.71 V ~ 1.96 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 56-LFCSP-VQ(8x8)
包裝: 托盤
產(chǎn)品目錄頁面: 552 (CN2011-ZH PDF)
AD9959
Rev. B | Page 6 of 44
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Residual Phase Noise @ 100.3 MHz (fOUT)
with REFCLK Multiplier Enabled 5×
@ 1 kHz Offset
120
dBc/Hz
@ 10 kHz Offset
130
dBc/Hz
@ 100 kHz Offset
135
dBc/Hz
@ 1 MHz Offset
129
dBc/Hz
Residual Phase Noise @ 15.1 MHz (fOUT)
with REFCLK Multiplier Enabled 20×
@ 1 kHz Offset
127
dBc/Hz
@ 10 kHz Offset
136
dBc/Hz
@ 100 kHz Offset
139
dBc/Hz
@ 1 MHz Offset
138
dBc/Hz
Residual Phase Noise @ 40.1 MHz (fOUT)
with REFCLK Multiplier Enabled 20×
@ 1 kHz Offset
117
dBc/Hz
@ 10 kHz Offset
128
dBc/Hz
@ 100 kHz Offset
132
dBc/Hz
@ 1 MHz Offset
130
dBc/Hz
Residual Phase Noise @ 75.1 MHz (fOUT)
with REFCLK Multiplier Enabled 20×
@ 1 kHz Offset
110
dBc/Hz
@ 10 kHz Offset
121
dBc/Hz
@ 100 kHz Offset
125
dBc/Hz
@ 1 MHz Offset
123
dBc/Hz
Residual Phase Noise @ 100.3 MHz (fOUT)
with REFCLK Multiplier Enabled 20×
@ 1 kHz Offset
107
dBc/Hz
@ 10 kHz Offset
119
dBc/Hz
@ 100 kHz Offset
121
dBc/Hz
@ 1 MHz Offset
119
dBc/Hz
SERIAL PORT TIMING CHARACTERISTICS
Maximum Frequency Serial Clock (SCLK)
200
MHz
Minimum SCLK Pulse Width Low (tPWL)
1.6
ns
Minimum SCLK Pulse Width High (tPWH)
2.2
ns
Minimum Data Setup Time (tDS)
2.2
ns
Minimum Data Hold Time
0
ns
Minimum CS Setup Time (tPRE)
1.0
ns
Minimum Data Valid Time for Read Operation
12
ns
MISCELLANEOUS TIMING CHARACTERISTICS
MASTER_RESET Minimum Pulse Width
1
Min pulse width = 1 sync clock period
I/O_UPDATE Minimum Pulse Width
1
Min pulse width = 1 sync clock period
Minimum Setup Time (I/O_UPDATE to SYNC_CLK)
4.8
ns
Rising edge to rising edge
Minimum Hold Time (I/O_UPDATE to SYNC_CLK)
0
ns
Rising edge to rising edge
Minimum Setup Time (Profile Inputs to SYNC_CLK)
5.4
ns
Minimum Hold Time (Profile Inputs to SYNC_CLK)
0
ns
Minimum Setup Time (SDIO Inputs to SYNC_CLK)
2.5
ns
Minimum Hold Time (SDIO Inputs to SYNC_CLK)
0
ns
Propagation Time Between REF_CLK and SYNC_CLK
2.25
3.5
5.5
ns
Profile Pin Toggle Rate
2
Sync
clocks
CMOS LOGIC INPUTS
VIH
2.0
V
VIL
0.8
V
Logic 1 Current
3
12
μA
Logic 0 Current
12
μA
Input Capacitance
2
pF
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