參數(shù)資料
型號: AD9959BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 12/44頁
文件大?。?/td> 0K
描述: IC DDS QUAD 10BIT DAC 56LFCSP
產(chǎn)品培訓模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設計資源: Phase Coherent FSK Modulator (CN0186)
標準包裝: 1
分辨率(位): 10 b
主 fclk: 500MHz
調(diào)節(jié)字寬(位): 32 b
電源電壓: 1.71 V ~ 1.96 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
供應商設備封裝: 56-LFCSP-VQ(8x8)
包裝: 托盤
產(chǎn)品目錄頁面: 552 (CN2011-ZH PDF)
AD9959
Rev. B | Page 2 of 44
TABLE OF CONTENTS
REVISION HISTORY
7/08—Rev. A to Rev. B
Added Pin Profile Toggle Rate Parameter in Table 1................... 6
Changes to Figure 24...................................................................... 14
Changes to Figure 31...................................................................... 17
Changes to Reference Clock Input Circuitry Section................ 20
Changes to Operation Section ...................................................... 29
Changes to Figure 40...................................................................... 30
Changes to Serial Data I/O (SDIO_0, SDIO_1, SDIO_3)
Section.............................................................................................. 32
Changes to Table 38........................................................................ 43
Added Exposed Pad Notation to Outline Dimensions ............. 44
3/08—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Inserted Figure 1 ............................................................................... 1
Changes to Input Level Specification............................................. 4
Changes to Layout ............................................................................ 8
Changes to Table 3............................................................................ 9
Added Equivalent Input and Output Circuits Section .............. 17
Changes to Figure 35...................................................................... 21
Changes to Setting the Slope of the Linear Sweep Section ....... 25
Changes to Frequency Linear Sweep Example: AFP Bits = 10
Section.............................................................................................. 26
Changes to Figure 37...................................................................... 26
Changes to Figure 38 and Figure 39............................................. 27
Added Table 25 ............................................................................... 31
Changes to Figure 41...................................................................... 31
Changes to Figure 42...................................................................... 32
Added Example Instruction Byte Section ................................... 32
Added Table 27 ............................................................................... 33
Changes to Figure 46, Figure 47, Figure 48, and Figure 49....... 35
Changes to Register Maps and Bit Descriptions Section .......... 36
Added Endnote 1 to Table 30........................................................ 38
Changes to Ordering Guide .......................................................... 44
7/05—Revision 0: Initial Version
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