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參數(shù)資料
| 型號： | AD9959BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 33/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS QUAD 10BIT DAC 56LFCSP |
| 產(chǎn)品培訓模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設計資源： | Phase Coherent FSK Modulator (CN0186) |
| 標準包裝： | 1 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 500MHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.71 V ~ 1.96 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
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AD9959
Rev. B | Page 39 of 44
DESCRIPTIONS FOR CONTROL REGISTERS
Channel Select Register (CSR)—Address 0x00
One byte is assigned to this register.
The CSR determines if channels are enabled or disabled by the status of the four channel enable bits. All four channels are enabled by
their default state. The CSR also determines which serial mode of operation is selected. In addition, the CSR offers a choice of MSB first
or LSB first format.
Table 31. Bit Descriptions for CSR
Bit
Mnemonic
Description
7:4
Channel [3:0] enable
Bits are active immediately after being written. They do not require an I/O update to take effect.
There are four sets of channel registers and profile (channel word) registers, one per channel. This
is not shown in the channel register map or the profile register map. The addresses of all channel
registers and profile registers are the same for each channel. Therefore, the channel enable bits
distinguish the channel registers and profile registers values of each channel. For example,
1001 = only Channel 3 and Channel 0 receive commands from the channel registers and profile
registers.
0010 = only Channel 1 receives commands from the channel registers and profile registers.
3
Must be 0
Must be set to 0.
2:1
Serial I/O mode select
00 = single-bit serial (2-wire mode).
01 = single-bit serial (3-wire mode).
10 = 2-bit serial mode.
11 = 4-bit serial mode.
See the Serial I/O Modes of Operation section for more details.
0
LSB first
0 = the serial interface accepts serial data in MSB first format (default).
1 = the serial interface accepts serial data in LSB first format.
Function Register 1 (FR1)—Address 0x01
Three bytes are assigned to this register. FR1 is used to control the mode of operation of the chip.
Table 32. Bit Descriptions for FR1
Bit
Mnemonic
Description
23
VCO gain control
0 = the low range (system clock below 160 MHz) (default).
1 = the high range (system clock above 255 MHz).
22:18
PLL divider ratio
If the value is 4 or 20 (decimal) or between 4 and 20, the PLL is enabled and the value sets the
multiplication factor. If the value is outside of 4 and 20 (decimal), the PLL is disabled.
17:16
Charge pump control
00 (default) = the charge pump current is 75 μA.
01 = charge pump current is 100 μA.
10 = charge pump current is 125 μA.
11 = charge pump current is 150 μA.
15
Open
14:12
Profile pin configuration (PPC)
The profile pin configuration bits control the configuration of the data and SDIO_x pins for the
different modulation modes. See the Modulation Mode section in this document for details.
11:10
Ramp-up/ramp-down (RU/RD)
The RU/RD bits control the amplitude ramp-up/ramp-down time of a channel. See the Output
Amplitude Control Mode section for more details.
9:8
Modulation level
The modulation (FSK, PSK, and ASK) level bits control the level (2/4/8/16) of modulation to be
performed for a channel. See the Modulation Mode section for more details.
7
Reference clock input
0 = the clock input circuitry is enabled for operation (default).
power-down
1 = the clock input circuitry is disabled and is in a low power dissipation state.
6
External power-down mode
0 = the external power-down mode is in fast recovery power-down mode (default). In this mode,
when the PWR_DWN_CTL input pin is high, the digital logic and the DAC digital logic are
powered down. The DAC bias circuitry, PLL, oscillator, and clock input circuitry are not powered
down.
1 = the external power-down mode is in full power-down mode. In this mode, when the
PWR_DWN_CTL input pin is high, all functions are powered down. This includes the DAC and PLL,
which take a significant amount of time to power up.
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相關代理商/技術參數(shù) |
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| AD9959BCPZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
| AD9959BCPZ-REEL7 | 功能描述:IC DDS QUAD 10BIT DAC 56LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9959BCPZ-REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
| AD995PCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| AD9960BSTZ | 功能描述:RFID應答器 MxFE for RFID Reader Transceiver RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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