參數(shù)資料
型號: AD9959BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 38/44頁
文件大?。?/td> 0K
描述: IC DDS QUAD 10BIT DAC 56LFCSP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計資源: Phase Coherent FSK Modulator (CN0186)
標(biāo)準(zhǔn)包裝: 1
分辨率(位): 10 b
主 fclk: 500MHz
調(diào)節(jié)字寬(位): 32 b
電源電壓: 1.71 V ~ 1.96 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 56-LFCSP-VQ(8x8)
包裝: 托盤
產(chǎn)品目錄頁面: 552 (CN2011-ZH PDF)
AD9959
Rev. B | Page 43 of 44
Linear Sweep Ramp Rate (LSRR)—Address 0x07
Two bytes are assigned to this register.
Table 38. Description for LSRR
Bit
Mnemonic
Description
15:8
Falling sweep ramp rate (FSRR)
Linear falling sweep ramp rate.
7:0
Rising sweep ramp rate (RSRR)
Linear rising sweep ramp rate.
LSR Rising Delta Word (RDW)—Address 0x08
Four bytes are assigned to this register.
Table 39. Description for RDW
Bit
Mnemonic
Description
31:0
Rising delta word
32-bit rising delta-tuning word.
LSR Falling Delta Word (FDW)—Address 0x09
Four bytes are assigned to this register.
Table 40. Description for FDW
Bit
Mnemonic
Description
31:0
Falling delta word
32-bit falling delta-tuning word.
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