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參數(shù)資料
| 型號： | AD9959BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS QUAD 10BIT DAC 56LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計資源： | Phase Coherent FSK Modulator (CN0186) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 500MHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.71 V ~ 1.96 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
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AD9959
Rev. B | Page 10 of 44
Pin No.
Mnemonic
Description
24
CLK_MODE_SEL
I
Control Pin for the Oscillator Section. Caution: Do not drive this pin beyond 1.8 V.
When high (1.8 V), the oscillator section is enabled to accept a crystal as the
REF_CLK source. When low, the oscillator section is bypassed.
27
LOOP_FILTER
I
Connects to the external zero compensation network of the PLL loop filter.
Typically, the network consists of a 0 Ω resistor in series with a 680 pF capacitor
tied to AVDD.
29
CH0_IOUT
O
Complementary DAC Output. Terminates into AVDD.
30
CH0_IOUT
O
True DAC Output. Terminates into AVDD.
35
CH1_IOUT
O
Complementary DAC Output. Terminates into AVDD.
36
CH1_IOUT
O
True DAC Output. Terminates into AVDD.
40 to 43
P0 to P3
I
Data pins used for modulation (FSK, PSK, ASK), to start/stop the sweep accumulators
or used to ramp up/ramp down the output amplitude. The data is synchronous to
the SYNC_CLK (Pin 54). The data inputs must meet the setup and hold time
requirements of the SYNC_CLK. The functionality of these pins is controlled by the
profile pin configuration (PPC) bits (FR1[14:12]).
46
I/O_UPDATE
I
A rising edge transfers data from the serial I/O port buffer to active registers.
I/O_UPDATE is synchronous to the SYNC_CLK (Pin 54). I/O_UPDATE must meet the
setup and hold time requirements of the SYNC_CLK to guarantee a fixed pipeline
delay of data to the DAC output; otherwise, a ±1 SYNC_CLK period of pipeline
uncertainty exists. The minimum pulse width is one SYNC_CLK period.
47
CS
I
Active Low Chip Select. Allows multiple devices to share a common I/O bus (SPI).
48
SCLK
I
Serial Data Clock for I/O Operations. Data bits are written on the rising edge of
SCLK and read on the falling edge of SCLK.
49
DVDD_I/O
I
3.3 V Digital Power Supply for SPI Port and Digital I/O.
50
SDIO_0
I/O
Data Pin SDIO_0 is dedicated to the serial port I/O only.
51, 52
SDIO_1, SDIO_2
I/O
Data Pin SDIO_1 and Data Pin SDIO_2 can be used for the serial I/O port or used to
initiate a ramp-up/ramp-down (RU/RD) of the DAC output amplitude.
53
SDIO_3
I/O
Data Pin SDIO_3 can be used for the serial I/O port or to initiate a ramp-up/ramp-down
(RU/RD) of the DAC output amplitude. In single-bit or 2-bit modes, SDIO_3 is used
for SYNC_I/O. If the SYNC_I/O function is not used, tie to ground or Logic 0. Do not
let SDIO_3 float in single-bit or 2-bit modes.
54
SYNC_CLK
O
The SYNC_CLK runs at one-fourth the system clock rate; it can be disabled. I/O_UPDATE
or data (Pin 40 to Pin 43) is synchronous to the SYNC_CLK. To guarantee a fixed pipeline
delay of data to DAC output, I/O_UPDATE or data (Pin 40 to Pin 43) must meet the
setup and hold time requirements to the rising edge of SYNC_CLK; otherwise, a ±1
SYNC_CLK period of uncertainty occurs.
1 I = input, O = output.
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| AD9959BCPZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
| AD9959BCPZ-REEL7 | 功能描述:IC DDS QUAD 10BIT DAC 56LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9959BCPZ-REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
| AD995PCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| AD9960BSTZ | 功能描述:RFID應(yīng)答器 MxFE for RFID Reader Transceiver RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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