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參數(shù)資料
| 型號(hào)： | AD9954YSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/40頁 |
| 文件大小： | 0K |
| 描述： | IC DDS DAC 14BIT 1.8V 48-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 400MHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.71 V ~ 1.96 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP 裸露焊盤（7x7） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
| 配用： | AD9954/PCBZ-ND - BOARD EVAL FOR 9954 |
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AD9954
Rev. B | Page 13 of 40
THEORY OF OPERATION
COMPONENT BLOCKS
REFCLK Input
The AD9954 supports several methods for generating the
internal system clock. An on-chip oscillator circuit is available
for initiating the low frequency reference signal by connecting a
crystal to the clock input pins. The system clock can be generated
using an internal, PLL-based reference clock multiplier, allowing
the part to operate with a low frequency clock source while still
providing a high sample rate for the DDS and DAC. For best
phase noise performance, a clean, stable clock with a high slew
rate should be used to drive the REFCLK pin and bypass the
multiplier.
The available modes are configured using the CLKMODESELECT
pin, CFR1<4> and CFR2<7:3>. Note that the CLKMODESELECT
pin is a 1.8 V logic only and does not apply to 3.3 V logic.
Pulling CLKMODESELECT high enables the on-chip crystal
oscillator circuit. With the on-chip oscillator enabled, users of
the AD9954 connect an external crystal to the REFCLK and
REFCLK inputs to produce a low frequency reference clock (see
Table 1 for the crystal frequency range supported). The signal
generated by the oscillator is buffered, and then delivered to the
rest of the chip. This buffered signal is provided on the
CRYSTAL OUT pin.
When the internal oscillator is disabled, an external oscillator
must provide the REFCLK and/or REFCLK signals. For differential
operation, these pins are driven with complementary signals. For
single-ended operation, a 0.1 μF capacitor should be connected
between the unused pin and the analog power supply. With the
capacitor in place, the clock input pin bias voltage is 1.35 V.
Table 5 summarizes the clock modes of operation. Note the PLL
multiplier is controlled via the CFR2<7:3> bits, independent of
the CFR1<4> bit.
Clock Multiplier
An on-board PLL allows multiplication of the REFCLK
frequency. The multiplication factor is set using CFR2<7:3>.
When programmed for values ranging from 0x04 to 0x14
(decimal 4 to 20), the PLL multiplies the REFCLK input
frequency by the programmed value. The user must consider the
specified maximum frequency for the PLL when programming. If
the multiplication factor is changed, the user must allocate time
to allow the PLL to lock (approximately 1 ms).
The PLL is bypassed by programming a value outside the range
of 4 to 20 (decimal). When bypassed, the PLL is shut down to
conserve power.
The VCO in the PLL has a selectable frequency range. Use the
VCO range bit (CFR2<2>) to set the appropriate range.
The PLL in the clock multiplier has a loop filter comprised
of on-chip components as well as external components.
Recommended values for the external resistor/capacitor
are provided in Table 4.
Table 4. External Loop Filter Components for Clock Multiplier
Multiply Value
Resistor Value
Capacitor Value (μF)
4×
0 Ω
0.1
10×
1 kΩ
0.1
20×
243 Ω
0.01
DAC Output
Unlike many DACs, the DAC output on the AD9954 is referenced
to AVDD, not AGND.
Two complementary outputs provide a combined full-scale
output current (IOUT). Differential outputs reduce the amount of
common-mode noise that may be present at the DAC output,
resulting in a better signal-to-noise ratio. The full-scale current
is controlled by means of an external resistor (RSET) connected
between the DAC_RSET pin and the DAC ground pin (Pin 49,
the exposed paddle). The full-scale current is proportional to
the resistor value by the equation
Ω
39.19/
OUT
SET
I
R
The maximum full-scale output current of the combined
DAC outputs is 15 mA. Limiting the output to 10 mA
maximum provides the best spurious-free dynamic range
(SFDR) performance. The DAC output compliance range is
AVDD + 0.5 V to AVDD 0.5 V. Voltages developed beyond
this range result in excessive DAC distortion and could potentially
damage the DAC output circuitry. Proper attention should be
paid to the load termination to keep the output voltage within
this compliance range.
Table 5. Clock Input Modes of Operation
CFR1<4>
CLKMODESELECT
CFR2<7:3>
Oscillator Enabled?
System Clock
Frequency Range (MHz)
Low
High
4 ≤ M ≤ 20
Yes
fCLK = fOSC × M
80 < fCLK < 400
Low
High
M < 4 or M > 20
Yes
fCLK = fOSC
20 < fCLK < 30
Low
4 ≤ M ≤ 20
No
fCLK = fOSC × M
80 < fCLK < 400
Low
M < 4 or M > 20
No
fCLK = fOSC
10 < fCLK < 400
High
X
No
fCLK = 0
N/A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9954YSVZ | 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9954 TQFP48 |
| AD9954YSVZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
| AD9954YSVZ-REEL7 | 功能描述:IC DDS DAC 14BIT 1.8V 48TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9954YSVZ-REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
| AD9955KS6 | 制造商:AD 功能描述:* |
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