參數(shù)資料
型號： AD9954YSVZ
廠商： Analog Devices Inc
文件頁數(shù)： 19/40頁
文件大?。?/td> 0K
描述： IC DDS DAC 14BIT 1.8V 48-TQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 14 b
主 fclk： 400MHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.71 V ~ 1.96 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-TQFP 裸露焊盤（7x7）
包裝： 托盤
產(chǎn)品目錄頁面： 552 (CN2011-ZH PDF)
配用： AD9954/PCBZ-ND - BOARD EVAL FOR 9954
AD9954
Rev. B | Page 26 of 40
Table 12. Register Map—When Linear Sweep Enable Bit Is False (CFR1<21> = 0)
Note that the RAM Enable Bit CFR1<31> only activates the RAM itself, not the RAM segment control words.
Register
Name
(Serial
Address)
Bit
Range
(MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
Default
Value Or
Profile
Control
Function
Register
No.1
(CFR1)
(0x00)
<7:0>
Digital
Power-
Down
Comp
Power-
Down
DAC
Power-
Down
Clock
Input
Power-
Down
External
Power-
Down
Mode
Linear
Sweep
No-
Dwell
SYNC_CLK
Disable
Not
Used
0x00
<15:8>
SRR Load
Enable
AutoClr
Freq
Accum
AutoClr
Phase
Accum
Sine/
Cosine
Select
Clear
Freq
Accum
Clear
Phase
Accum
SDIO
Input
Only
LSB First
0x00
<23:16>
Automatic
Sync
Enable
Software
Manual
Sync
Linear
Sweep
Enable
Not Used
Not
Used
Not Used
Not
Used
0x00
<31:24>
RAM
Enable
RAM
Destination
Internal Profile Control<2:0>
Load ARR
Control
OSK
Enable
Auto
OSK
Enable
0x00
Control
Function
Register
No. 2
(CFR2)
(0x01)
<7:0>
REFCLK Multiplier
VCO
Range
Charge Pump
Current<1:0>
0x00
<15:8>
Not Used
High
Speed
Sync
Enable
Hardware
Manual
Sync
Enable
XTAL
OUT
Enable
Not
Used
0x00
<23:16>
Not Used
0x18
Amplitude
Scale
Factor (ASF)
(0x02)
<7:0>
Amplitude Scale Factor Register<7:0>
0x00
<15:8>
Auto Ramp Rate
Speed Control<1:0>
Amplitude Scale Factor Register<13:8>
0x00
Amplitude
Ramp Rate
(ARR)
(0x03)
<7:0>
Amplitude Ramp Rate Register<7:0>
0x00
Frequency
Tuning
Word
(FTW0)
(0x04)
<7:0>
Frequency Tuning Word No. 0<7:0>
0x00
<15:8>
Frequency Tuning Word No. 0<15:8>
0x00
<23:16>
Frequency Tuning Word No. 0<23:16>
0x00
<31:24>
Frequency Tuning Word No. 0<31:24>
0x00
Phase
Offset Word
(POW0)
(0x05)
<7:0>
Phase Offset Word No. 0<7:0>
0x00
<15:8>
Not Used<1:0>
Phase Offset Word No. 0<13:8>
0x00
Frequency
Tuning
Word
(FTW1)
(0x06)
<7:0>
Frequency Tuning Word No. 1<7:0>
0x00
<15:8>
Frequency Tuning Word No. 1<15:8>
0x00
<23:16>
Frequency Tuning Word No. 1<23:16>
0x00
<31:24>
Frequency Tuning Word No. 1<31:24>
0x00
Profile 0
RAM
Segment
Control
Word No. 0
(RSCW0)
(0x07)
<7:0>
RAM Segment 0 Mode
Control<2:0>
No-Dwell
Active
RAM Segment 0 Beginning Address<9:6>
PS0 = 0
PS1 = 0
<15:8>
RAM Segment 0 Beginning Address<5:0>
RAM Segment 0
Final Address<9:8>
PS0 = 0
PS1 = 0
<23:16>
RAM Segment 0 Final Address<7:0>
PS0 = 0
PS1 = 0
<31:24>
RAM Segment 0 Address Ramp Rate<15:8>
PS0 = 0
PS1 = 0
<39:32>
RAM Segment 0 Address Ramp Rate<7:0>
PS0 = 0
PS1 = 0
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參數(shù)描述
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